Instruction flow-based front-end throttling for power-aware high-performance processors

Abstract

We present a number of power-aware instruction front-end (fetch/decode) throttling methods for high-performance dynamically-scheduled superscalar processors. Our methods reduce power dissipation by selectively turning on and off instruction fetch and decode. Moreover, they have a negligible impact on performance as they deliver instructions just in time for exploiting the available parallelism. Previously proposed front-end throttling methods rely on branch prediction confidence estimation. We introduce a new class of methods that exploit information about instruction flow (rate of instructions passing through stages). We show that our methods can boost power savings over previously proposed methods. In particular, for an 8-way processor a combined method reduces traffic by 14%, 20%, 6% and 6% for the fetch, decode, issue and complete stages respectively while performance remains mostly unaffected. The best previously proposed method reduces traffic by 10%, 15%, 4% and 4% respectively.

Processor reliability enhancement through compiler-directed register file peak temperature reduction

“…Using these models, two types of architectural Dynamic Thermal Management (DTM) techniques have been proposed to prevent the chip from reaching critical temperature levels. Temporal techniques slow down heat accumulation either at fine granularity through fetch toggling [10], decode throttling [13], frequency and voltage scaling [6], or at coarse granularity through periodically stopping the computation to induce cooling [14]. Obviously, slowing down or stopping the entire computation engenders significant performance degradation.…”

Energy efficient co-adaptive instruction fetch and issue

“…As noted in prior work [4,17,18,23], instruction delivery power is higher than necessary because of the performance focused design strategy at the high end. In such designs, the front-end fetch mechanism provides instructions using the peak architected bandwidth, as early as possible, by making use of sophisticated branch prediction algorithms.…”

“…Other methods of fetch gating [4,17] attempt to reduce idle energy by making the fetch mechanism more demanddriven; that is, instruction fetch is gated when the downstream utilization is high or the flow rate mismatch (between decode and commit) is high. In this context of flow rate matching, the issue queue plays a central role for two reasons.…”

Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors

“…In case of low confidence, they gate the pipeline by stalling instruction fetch. Baniasadi and Moshovos [2] extend this approach to throttle the execution of instruction flow in wide-issue super-scalar processors to achieve energy reduction. They use instruction flow information such as rate of instructions passing through stages to determine whether to stall stages.…”