Inspection of high-aspect ratio layers at sub 20nm node

Vikram, Abhishek; Lin, Kuan; Camp, Janay; Kini, Sumanth; Jin, Frank; Venkatesan, Vinod

doi:10.1117/12.2011574

Cited by 9 publications

(2 citation statements)

References 3 publications

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“…Secondly, the dishing depth varies depending on metal volume and density distribution that is caused by chip layout, which leads to potential weak points. To address the problems, our previous work (Figure . 8) demonstrated the implementation of an inline metrology to precisely measure VIA location and its depth of dishing and protrusion, ensuring better CMP process control by utilizing pattern centric solution [12] . Yet the long measurement duration severely limits the application of AFM in mass production [13] .…”

Section: X-tackingmentioning

confidence: 99%

Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

Zhang¹,

Xu²,

Wang³

et al. 2019

Journal of Microelectronic Manufacturing

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3D NAND technical development and manufacturing face many challenges to scale down their devices, and metrology stands out as much more difficult at each turn. Unlike planar NAND, 3D NAND has a three-dimensional vertical structure with high-aspect ratio. Obviously top-down images is not enough for process control, instead inner structure control becomes much more important than before, e.g. channel hole profiles. Besides, multi-layers, special materials and YMTC unique X-Tacking technology also bring other metrology challenges: high wafer bow, stress induced overlay, opaque film measurement. Technical development can adopt some destructive methodology (TEM, etch-back SEM), while manufacturing can only use nondestructive method. These drive some new metrology development, including X-Ray, mass measure and Mid-IR spectroscopy. As 3D NAND suppliers move to >150 layers devices, the existing metrology tools will be pushed to the limits. Still, the metrology must innovate.

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Section: X-tackingmentioning

confidence: 99%

Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

Zhang¹,

Xu²,

Wang³

et al. 2019

Journal of Microelectronic Manufacturing

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show abstract

“…As double patterning, triple patterning, or even quadruple patterning ultraviolet (UV) lithography are now widely used, the number of inspection steps scales up with the increase of patterning steps, which potentially decreases the throughput and increases the risk of device failure because the missed defect detection events will be transferred to the end process. To make things worse, the extremely complex fin field-effect transistor and gate-all-around nanowire devices are now employed to reduce leakage current and improve device's stability beyond the technology node of 22 nm [3], which, results in the fact that the key defects of interest in this three-dimensional (3D) architectures are typically sub-surface (especially voids), buried in the stack, or are residues in high aspect ratio structures [4]. Overall, as the industry starts largescale sub-10 nm high-volume manufacturing, there is greater awareness that defects introduced by original equipment manufacturer components impact yield and manufacturing costs.…”

Section: Introductionmentioning

confidence: 99%

Optical wafer defect inspection at the 10 nm technology node and beyond

Zhu¹,

Liu²,

Xu³

et al. 2022

Int. J. Extrem. Manuf.

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The growing demand for electronic devices, smart devices, and the Internet of Things constitutes the primary driving force for marching down the path of decreased critical dimension and increased circuit intricacy of integrated circuits. However, as sub-10 nm high-volume manufacturing is becoming the mainstream, there is greater awareness that defects introduced by original equipment manufacturer components impact yield and manufacturing costs. The identification, positioning, and classification of these defects, including random particles and systematic defects, are becoming more and more challenging at the 10 nm node and beyond. Very recently, the combination of conventional optical defect inspection with emerging techniques such as nanophotonics, optical vortices, computational imaging, quantitative phase imaging, and deep learning is giving the field a new possibility. Hence, it is extremely necessary to make a thorough review for disclosing new perspectives and exciting trends, on the foundation of former great reviews in the field of defect inspection methods. In this article, we give a comprehensive review of the emerging topics in the past decade with a focus on three specific areas: (1) the defect detectability evaluation, (2) the diverse optical inspection systems, and (3) the post-processing algorithms. We hope, this work can be of importance to both new entrants in the field and people who are seeking to use it in interdisciplinary work.

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Application of backscattered electron imaging for process development in advanced technology nodes

Lei

Nguyen

et al. 2015

2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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Inspection of high-aspect ratio layers at sub 20nm node

Cited by 9 publications

References 3 publications

Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

Optical wafer defect inspection at the 10 nm technology node and beyond

Application of backscattered electron imaging for process development in advanced technology nodes

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