Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

Zhang, Wei; Xu, Jun; Wang, Sicong; Zhou, Yi; Jing, Mi

doi:10.33079/jomm.20030102

Cited by 7 publications

(4 citation statements)

References 14 publications

(14 reference statements)

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“…Figure 12c,d sh the relationship between the current of the V-TFT prepared memory and the variati Retention time and Pulse width. Otherwise, YANGTZE River Storage company used unique and innovative X-tac storage architecture with 3D NAND [65], this structure also has a vertical channel ductivity direction, and vertical structures are used in memory devices, which is a m direction for future development. Combining V-TFT with 3D NAND storage techno will lead to more meaningful development of device properties.…”

Section: R Peer Reviewmentioning

confidence: 99%

Research Progress of Vertical Channel Thin Film Transistor Device

Sun

Huang

Wen

et al. 2023

Sensors

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Thin film transistors (TFTs) as the core devices for displays, are widely used in various fields including ultra-high-resolution displays, flexible displays, wearable electronic skins and memory devices, especially in terms of sensors. TFTs have now started to move towards miniaturization. Similarly to MOSFETs problem, traditional planar structure TFTs have difficulty in reducing the channel’s length sub-1μm under the existing photolithography technology. Vertical channel thin film transistors (V-TFTs) are proposed. It is an effective solution to overcome the miniaturization limit of traditional planar TFTs. So, we summarize the different aspects of VTFTs. Firstly, this paper introduces the structure types, key parameters, and the impact of different preparation methods in devices of V-TFTs. Secondly, an overview of the research progress of V-TFTs’ active layer materials in recent years, the characteristics of V-TFTs and their application in examples has proved the enormous application potential of V-TFT in sensing. Finally, in addition to the advantages of V-TFTs, the current technical challenge and their potential solutions are put forward, and the future development trend of this new structure of V-TFTs is proposed.

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Section: R Peer Reviewmentioning

confidence: 99%

Research Progress of Vertical Channel Thin Film Transistor Device

Sun

Huang

Wen

et al. 2023

Sensors

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“…3D flash memory development and manufacturing has evolved rapidly in recent years as it continuously scales down the size of the devices [1,2]. This innovation, in return, brings lots of metrology challenges to the high-volume manufacturing process [3,4]. Spectroscopic ellipsometry is widely used to analyze the changes in intensity of reflected light to determine the shape and dimensions of peorodic structures in semiconductor metrology systems [5][6][7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Leveraging x-ray scatterometry and machine learning to enable robust and high-throughput optical critical dimension metrology for advanced 3D flash memory contact hole profile

Chouaib,

Shi,

Chou

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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3D flash memory structures have been rapidly developed over the past decade to achieve a high density of stacked memory cells with periodic channel holes across the device. Small deviations of the hole shape can result in considerable variations in device performance and product yield. Understanding the behavior and performance of these high-aspect-ratio structures plays a vital role in such complex vertically stacked structures. Memory hole critical dimensions (CDs) serve as the key information to evaluate the performance of 3D flash memory devices, and these CDs are typically measured by rigorous coupled wave analysis (RCWA) based optical metrology that requires costly and destructive scanning electron microscopy (SEM) or transmission electron microscopy (TEM) reference.Here, we utilize critical dimension smallangle X-ray scatterometry (CD-SAXS) that provides reliable and nondestructive ground truth reference to extract a large amount of detailed hole shape information within a practical time scale compared to traditional lengthy TEM measurements. We leverage advanced data analytics and machine learning techniques to enable an optical critical dimension metrology solution along with the desired amount of reference from CD-SAXS measurements for the memory hole profile investigation. This proposed methodology opens up a new venue for a high-throughput, robust and accurate hole CD profile measurement for the fast-paced and high-volume 3D flash memory manufacturing technology.

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“…The HAR etch process challenges are addressed by splitting the massive stack into two decks, that is, replacing one single etch step with two more manageable etch steps. Adoption of tier stacking (dual deck) leads to increasingly high aspect ratios and poses metrology challenges [2] in controlling overlay, tilt, and misalignment in the manufacturing processes for next generation 3D NAND devices.…”

Section: Introductionmentioning

confidence: 99%

Characterization of asymmetries in 3D NAND memory devices

Srivastava

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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The adoption of tier stacking (dual deck) leads to increasingly high aspect ratios and poses challenges in controlling overlay, tilt, and misalignment in the manufacturing processes for next generation 3D NAND devices. In this work we address metrology challenges such as tilt and overlay separation, measurement robustness influenced by process variation, and nonlinearity of spectral response to asymmetries. We show that Mueller measurement can separate overlay and tilt signals through distinct spectral response analyzed by a machine learning method with reference data. To reduce asymmetry measurement errors caused by process variation such as critical dimension (CD) and thickness changes, we propose and demonstrate improvement of tilt measurements on blind test wafers by feeding forward CD measurement results to the analysis of tilt signal. We also investigate nonlinear regression and show its capability to extend overlay measurement limit from linear response range, ±0.25pitch, to ±0.43pitch. In addition, for small structural asymmetries introduced by channel hole tilt, test RMSE is reduced by 20–40% from nonlinear regression alone or combined with CD feed-forward. We demonstrate that spectroscopic Mueller matrix measurements, paired with advanced machine learning analysis, provide nondestructive and accurate measurement of tilt, overlay, and misalignment for 3D NAND devices with high throughput and fast recipe creation.

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Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing

Cited by 7 publications

References 14 publications

Research Progress of Vertical Channel Thin Film Transistor Device

Research Progress of Vertical Channel Thin Film Transistor Device

Leveraging x-ray scatterometry and machine learning to enable robust and high-throughput optical critical dimension metrology for advanced 3D flash memory contact hole profile

Characterization of asymmetries in 3D NAND memory devices

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