Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

Pal, Ashish; Sachid, Angada B.; Gossner, Harald; Rao, V. Ramgopal

doi:10.1109/ted.2011.2109002

Cited by 108 publications

(38 citation statements)

References 17 publications

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“…(1) The Number of the TFET-Based Registers Since CMOS-and TFET-based SRAMs have similar size [29], we set the total amount of hybrid registers in each SM as the same as that (i.e. 16K) in the baseline case with default GPU configuration for the fair comparison.…”

Section: Methodsmentioning

confidence: 99%

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Tan

2013

International Symposium on Quality Electronic Design (ISQED)

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State-of-the-art General-Purpose computing on Graphics Processing Unit (GPGPU) is facing severe power challenge due to the increasing number of cores placed on a chip with decreasing feature size. In order to hide the long latency operations, GPGPU employs the fine-grained multithreading among numerous active threads, leading to the sizeable register files with massive power consumption. Exploring the optimal power savings in register files becomes the critical and first step towards the energyefficient GPGPUs. The conventional method to reduce dynamic power consumption is the supply voltage scaling, and the inter-bank tunneling FETs (TFETs) are the promising candidates compared to CMOS for low voltage operations regarding to both leakage and performance. However, always executing at the low voltage (so that low frequency) will result in significant performance degradation. In this study, we propose the hybrid CMOS-TFET based register files. To optimize the register power consumption, we allocate TFET-based registers to threads whose execution progress can be delayed to some degree to avoid the memory contentions with other threads, and the CMOS-based registers are still used for threads requiring normal execution speed. Our experimental results show that the proposed technique achieves 30% energy (including both dynamic and leakage) reduction in register files with little performance degradation compared to the baseline case equipped with naive power optimization technique.

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Section: Methodsmentioning

confidence: 99%

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Tan

2013

International Symposium on Quality Electronic Design (ISQED)

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“…In TFETs, at low V ds values or even at high V ds values, C gd comprises the major part of the gate capacitance (C gg ) unlike MOSFETs. Thus, C gd is the dominant component of gate capacitance, and this high value of C gd, (further enhanced due to Miller effect), poses a limitation on switching speed and power dissipation [27] of TFET based circuits. The limiting factor for attaining high cut-off frequency is the low value of trans-conductance and a high gate-todrain capacitance (C gd ).…”

Section: Capacitance Voltage Characteristicsmentioning

confidence: 99%

Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

Narang¹,

Saxena²,

Gupta³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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“…The simulation set up used in Sentaurus TCAD is calibrated against the previously reported data in [14], which is already calibrated against experimental data reported in [15]. For this purpose a device is prepared for simulation with dimensions as shown in [14].…”

Section: Simulation Set Upmentioning

confidence: 99%

“…For this purpose a device is prepared for simulation with dimensions as shown in [14]. Since the flat part of the I ds ÀV gs curve is due SRH recombination, therefore the carrier life times have been tuned in this part calibration.…”

Section: Simulation Set Upmentioning

confidence: 99%

“…Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply [14], for this calibration all physical dimensions are used from [14] and then the tuning for carriers' effective masses and life times is done to calibrate the results. voltage below 1 V is possible due to the absence of a subthresholdswing limit of 60 mV/decade.…”

Section: Previous Workmentioning

confidence: 99%

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