Insight on physics of Hf-based dielectrics reliability

Ribes, G.; Denais, M.; Bruyère, S.; Roy, D.; Monsieur, F.; Huard, V.; Parthasarthy, C.; Müller, Markus; Skotnicki, T.; Ghibaudo, G.

doi:10.1109/essder.2005.1546678

Cited by 5 publications

(5 citation statements)

References 3 publications

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“…(1). The extracted trap energies E i are on the order of 0.35 eV and 0.45 eV, close to the reported value of 0.35 eV obtained from detrapping measurements (12). The third extracted energy, E i < 0.01 eV, may correspond to the polaron-type motion of the electrons in the conduction band.…”

Section: Electrical Instability Due To Pre-existing Defectssupporting

confidence: 85%

Identifying Contributions to Electrical Instability in High-k Gate Stacks: As-Grown vs. Generated Defects

Bersuker¹,

Lysaght²,

Choi³

2007

ECS Trans.

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Stress-induced changes in the high-k gate stack electrical characteristics may originate in both the Hf-based dielectric film and the SiO2-like interfacial layer, in which instability could be induced by different mechanisms. In this work, we focus on the contributions from as-grown defects and defect precursors in each of these layers, as well as stress-generated defects, under low and high voltage stress regimes. Physical data, consistent with ab initio calculations, is presented in support of proposed theoretical explanations for the mechanisms that give rise to electrical performance.

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Section: Electrical Instability Due To Pre-existing Defectssupporting

confidence: 85%

Identifying Contributions to Electrical Instability in High-k Gate Stacks: As-Grown vs. Generated Defects

Bersuker¹,

Lysaght²,

Choi³

2007

ECS Trans.

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“…In order to characterize the hysteresis phenomena, we have proposed a novel time resolved measurement technique allowing the characterization of V t shift transients at short times [9]. In literature, other methods [10,11] have been proposed to extract the V t shift using the transconductance g m or its approximation via (V g -V t )/I d . However, both ECS Transactions, 35 (4) 773-804 (2011) techniques underestimate the V t shift (up to 50% in the worst cases), because they do not take into account the increase of g m as Id is reduced, or even underestimate gm.…”

Section: Trapping and Detrapping Mechanisms In Hfo 2 Filmsmentioning

confidence: 99%

Recent Findings in Electrical Behavior of CMOS High-K Dielectric/Metal Gate Stacks

et al. 2011

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We first review the kinetics of the trapping/detrapping process involved in hysteresis phenomena of HfO2 films on a large temperature range (20K-500K). We show that, up to 400K, trapping and detrapping processes are temperature independent after correction of threshold voltage variation with temperature. In most cases, the capture and emission into or from available traps are mainly controlled by tunneling. Then, we address the variations of the effective metal work function and its relation with the different fabrication processes. Based on C-V and internal photoemission measurements, we show the existence of an interfacial voltage drop (i.e. dipole) at the high-k SiO2 interface, as well as of variations in metal work function with metal gate process. Finally, we present a complete study of the transport mechanisms throughout the SiO2/HfO2 gate stacks combining C-V, I-V and Transmission Electron Microscopy measurements, on several nMOS transistors with different interfacial layer and HfO2 thicknesses, over a large temperature range (80K to 400K).

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“…The most acceptable one is that electrons are trapped by pre-existing traps when tunneling through the interface layer (IL) into the high-k bulk. [6][7][8][9] The second one is that stress induced defects transfer into traps and trap tunneling electrons. [10,11] The combination of the creation of an interface state with electron trapping is also proposed regarding the ultrathin gate dielectric.…”

Section: Introductionmentioning

confidence: 99%

Energy distribution extraction of negative charges responsible for positive bias temperature instability

Ren¹,

Yang²,

Wang³

et al. 2015

Chinese Phys. B

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A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of nMOSFET during positive bias temperature instability (PBTI) stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy, and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.

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Insight on physics of Hf-based dielectrics reliability

Abstract: In this work, we propose an analysis of trapping mechanism and we try to find the possible origins of the traps acting in the BTI stress. In a second section, we present a statistical and degradation analysis of breakdown for substrate and gate injections

Cited by 5 publications

References 3 publications

Identifying Contributions to Electrical Instability in High-k Gate Stacks: As-Grown vs. Generated Defects

Identifying Contributions to Electrical Instability in High-k Gate Stacks: As-Grown vs. Generated Defects

Recent Findings in Electrical Behavior of CMOS High-K Dielectric/Metal Gate Stacks

Energy distribution extraction of negative charges responsible for positive bias temperature instability

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