Innovative power gating for leakage reduction

Chowdhury, Masud H.; Gjanci, J.; Khaled, P.

doi:10.1109/iscas.2008.4541731

Cited by 18 publications

(10 citation statements)

References 9 publications

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“…Thus, multiple-stage enabling techniques in which several bundles of switches are sequentially turned on after a certain interval have been proposed [15], [16], [17], [18], [19]. More stages provide better in-rush-current control and IR drop but have the disadvantage of a longer turn-on time.…”

Section: Adaptive Two-stage Power Gating Strategy In a 3d Icmentioning

confidence: 99%

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Novel adaptive power gating strategy of TSV-based multi-layer 3D IC

Kim

Kang

Han

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

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Among power dissipation components, the leakage power has become more dominant with each successive technology node. A power gating technique has been widely used to reduce the standby leakage energy. In this work, we investigate the power gating strategy of TSV-based 3D IC stacking structures. Power gating control is becoming more complicated as more dies are stacked. We combine the on-chip PDN and TSV in a multilayered 3D IC for a power gating analysis of the static and dynamic voltage drops and in-rush current. Then, we propose a novel power gating strategy that optimizes the inrush current profile, subject to the voltage-drop constraints. Our power gating strategy provides a minimal wake-up latency such that the voltage noise safety margins are not violated. In addition, the layer dependency of the 3D IC on the power gating in terms of the wake-up time reduction is analyzed. We achieve an average wake-up time reduction of 28% for all cases with our adaptive power gating method that exploits location (or layer) information of the aggressors in a 3D IC.

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Section: Adaptive Two-stage Power Gating Strategy In a 3d Icmentioning

confidence: 99%

“…Therefore, many studies have been conducted to resolve the in-rush-current problems in power gated circuits. Multistage enabling algorithms have been suggested to limit the in-rush current by sequentially turning on the switches [15], [16], [17], [18], [19], [20]. Recently, a tokenbased adaptive power gating technique was proposed in [20].…”

Section: Introductionmentioning

confidence: 99%

Novel adaptive power gating strategy of TSV-based multi-layer 3D IC

Kim

Kang

Han

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

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“…NoCs naturally fit the GALS design paradigm by organizing groups of routers in different VFIs, where the size of each VFI is the knob to balance power and performance. Power gating (PG) [Chowdhury et al 2008] is another exploited actuator to face the excessive leakage power consumption since, to save power, it allows to switch a part of the logic off when in an idle state.…”

Section: Introductionmentioning

confidence: 99%

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

Zoni

Fornaciari

2015

J. Emerg. Technol. Comput. Syst.

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Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multicore revolution. One of the major design issues of multicore architectures is still the power, which can no longer be considered mainly due to the cores, since the NoC contribution to the overall energy budget is relevant. To face both static and dynamic power while balancing NoC performance, different actuators have been exploited in literature, mainly dynamic voltage frequency scaling (DVFS) and power gating. Typically, simulation-based tools are employed to explore the huge design space by adopting simplified models of the components. As a consequence, the majority of state-of-the-art on NoC power-performance optimization do not accurately consider timing and power overheads of actuators, or (even worse) do not consider them at all, with the risk of overestimating the benefits of the proposed methodologies.This article presents a simulation framework for power-performance analysis of multicore architectures with specific focus on the NoC. It integrates accurate power gating and DVFS models encompassing also their timing and power overheads. The value added of our proposal is manyfold: (i) DVFS and power gating actuators are modeled starting from SPICE-level simulations; (ii) such models have been integrated in the simulation environment; (iii) policy analysis support is plugged into the framework to enable assessment of different policies; (iv) a flexible GALS (globally asynchronous locally synchronous) support is provided, covering both handshake and FIFO re-synchronization schemas. To demonstrate both the flexibility and extensibility of our proposal, two simple policies exploiting the modeled actuators are discussed in the article.

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“…The additional PMOS transistor supports intermediate power-saving state-retaining modes at low supply voltage, and reduces ground bounce noise during transitions between normal and power-gated modes. Chowdhury et al [14] propose a similar trimode (i.e., RUN, HOLD, CUT-OFF) power gating technique using PMOS switches in parallel with NMOS footer switches, combined with additional NMOS switches in parallel with PMOS header switches. Finally, Zhang et al [15] propose a multi-mode power gating technique using three NMOS switches with different sizes and threshold voltages.…”

Section: Introductionmentioning

confidence: 99%

MAPG: Memory access power gating

Jeong

Kahng

Kang

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-In mobile systems, the problems of short battery life and increased temperature are exacerbated by wasted leakage power. Leakage power waste can be reduced by power-gating a core while it is stalled waiting for a resource. In this work, we propose and model memory access power gating (MAPG), a low-overhead technique to enable power gating of an active core when it stalls during a long memory access. We describe a programmable two-stage power gating switch design that can vary a core's wake-up delay while maintaining voltage noise limits and leakage power savings. We also model the processor power distribution network and the effect of memory access power gating on neighboring cores. Last, we apply our power gating technique to actual benchmarks, and examine energy savings and overheads from power gating stalled cores during long memory accesses. Our analyses show the potential for over 38% energy savings given "perfect" power gating on memory accesses; we achieve energy savings exceeding 20% for a practical, counter-based implementation.

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Innovative power gating for leakage reduction

Cited by 18 publications

References 9 publications

Novel adaptive power gating strategy of TSV-based multi-layer 3D IC

Novel adaptive power gating strategy of TSV-based multi-layer 3D IC

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

MAPG: Memory access power gating

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