MAPG: Memory access power gating

Jeong, Kwangok; Kahng, Andrew B.; Kang, Seokhyeong; Rosing, Tajana; Strong, Richard

doi:10.1109/date.2012.6176651

Cited by 2 publications

(3 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This allows the Level C to avoid unnecessary write operations every time a SA shift occurs. Furthermore, the memory banks of the SPM can be power gated using a single sleep-state transistor [32]. The dynamic management module controls the power gating and the flag offset along the memory banks.…”

Section: Proposed Me Memory System With Dynamic Managementmentioning

confidence: 99%

“…On the other hand, both sectors are turned on, and all the 384 memory banks are used. All memory banks can be power gated by the sleep-state transistors (ST), which are used as switches to shut off power supplies to memory banks [32]. When the memory banks corresponding to the sector are turned off, the stored data are lost since this data will no longer be necessary.…”

Section: Multi-sector Scratchpad Memory Designmentioning

confidence: 99%

See 1 more Smart Citation

Low-energy motion estimation memory system with dynamic management

Silveira

Amaral

Povala

et al. 2021

J Real-Time Image Proc

View full text Add to dashboard Cite

The digital video coding process imposes severe pressure on memory traffic, leading to considerable power consumption related to frequent DRAM accesses. External off-chip memory demand needs to be minimized by clever architecture/ algorithm co-design, thus saving energy and extending battery lifetime during video encoding. To exploit temporal redundancies among neighboring frames, the motion estimation (ME) algorithm searches for good matching between the current block and blocks within reference frames stored in external memory. To save energy during ME, this work performs memory accesses distribution analysis of the test zone search (TZS) ME algorithm and, based on this analysis, proposes both a multi-sector scratchpad memory design and dynamic management for the TZS memory access. Our dynamic memory management, called neighbor management, reduces both static consumption-by employing sectorlevel power gating-and dynamic consumption-by reducing the number of accesses for ME execution. Additionally, our dynamic management was integrated with two previously proposed solutions: a hardware reference frame compressor and the Level C data reuse scheme (using a scratchpad memory). This system achieves a memory energy consumption savings of 99.8% and, when compared to the baseline solution composed of a reference frame compressor and data reuse scheme, the memory energy consumption was reduced by 44.1% at a cost of just 0.35% loss in coding efficiency, on average. When compared with related works, our system presents better memory bandwidth/energy savings and coding efficiency results.

show abstract

Section: Proposed Me Memory System With Dynamic Managementmentioning

confidence: 99%

Section: Multi-sector Scratchpad Memory Designmentioning

confidence: 99%

Low-energy motion estimation memory system with dynamic management

Silveira

Amaral

Povala

et al. 2021

J Real-Time Image Proc

View full text Add to dashboard Cite

show abstract

“…Non-volatile flip-flops (NVFFs) are promising enablers of fine-grained power gating techniques because these circuits do not require a complex interface to transfer data from/to the external storage (e.g., SRAM) before powering down [1][2][3][4][5][6]. The NVFFs can sustain data without power supply.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Non-Volatile Flip-Flops Using Spin-Orbit-Torque (SOT) Magnetic Tunnel Junction Devices for High Integration and Low Energy Power-Gating Applications

Park

2020

Electronics

View full text Add to dashboard Cite

This paper presents two novel hybrid non-volatile flip-flops (NVFFs) comprised of the conventional CMOS flip-flop for static storage in normal operations and Spin-Orbit-Torque Magnetic Tunnel Junction (SOT-MTJ) devices for temporary storage during power gating. The proposed NVFFs re-utilize a part of the standard CMOS flip-flop infrastructure for storing and restoring data onto MTJs for reducing the area. Furthermore, the proposed NVFFs re-use a write current, which is used for storing an MTJ, to write the other MTJ at a time, resulting in 50% storing energy reduction. To reduce the area further, the number of external terminals of an MTJ is reduced by shorting the shorting physical terminals. Removing a terminal using the proposed STT-Like SOT configuration results in fewer transistors to control. The proposed NVFF circuits are evaluated using a compact MTJ model targeting implementation in a 14-nm technology node. Analysis indicates that area overheads are only 10.3% and 6.9% compared to the conventional D flip-flop because three or two minimum-sized NMOS transistors are added for accessing MTJs. Compared to the best previously known NVFFs, the proposed NVFF has an improvement by a factor of 2–8 in terms of the area overhead.

show abstract

MAPG: Memory access power gating

Cited by 2 publications

References 18 publications

Low-energy motion estimation memory system with dynamic management

Low-energy motion estimation memory system with dynamic management

Hybrid Non-Volatile Flip-Flops Using Spin-Orbit-Torque (SOT) Magnetic Tunnel Junction Devices for High Integration and Low Energy Power-Gating Applications

Contact Info

Product

Resources

About