InFO_oS (Integrated Fan-Out on Substrate) Technology for Advanced Chiplet Integration

Monolithic three‐dimensional integration of aligned carbon nanotube transistors for high‐performance integrated circuits

“…Three‐dimensional (3D) integrated circuit (IC) technology is becoming an alternative approach to the mainstream scaling‐down mode of modern ICs, especially in applications of high‐bandwidth near‐memory computing and fully functional systems on chips (SoCs) 1–7 . In parallel with the conventional geometry scaling mode in past decades, vertical multilayer integration of transistors and metal lines at different scales has emerged, and some methods have gradually evolved into a key technology in the semiconductor industry.…”

“…As a feasible solution for multilayer integration, through silicon vias (TSVs) have been widely adopted in multilayer DRAM chip integration, composing high bandwidth memory (HBM) with the record memory density at a high access speed 1,2 . The input and output (I/O) channels delivering massive data flow are located in the silicon interposer or embedded silicon bridge fabricated with state‐of‐the‐art back‐end‐of‐line (BEOL) multilayer metal lines, which is an essential 2.5D packaging paradigm 3–5 . However, the large gap between the sizes of transistors and TSVs not only limits the further promotion of integration granularity and interconnection density 6 but also brings about significant RC delay and heat dissipation 7 …”

“…Three-dimensional (3D) integrated circuit (IC) technology is becoming an alternative approach to the mainstream scaling-down mode of modern ICs, especially in applications of high-bandwidth near-memory computing and fully functional systems on chips (SoCs). [1][2][3][4][5][6][7] In parallel with the conventional geometry scaling mode in past decades, vertical multilayer integration of transistors and metal lines at different scales has emerged, and some methods have gradually evolved into a key technology in the semiconductor industry. As a feasible solution for multilayer integration, through silicon vias (TSVs) have been widely adopted in multilayer DRAM chip integration, composing high bandwidth memory (HBM) with the record memory density at a high access speed.…”

“…1,2 The input and output (I/O) channels delivering massive data flow are located in the silicon interposer or embedded silicon bridge fabricated with state-ofthe-art back-end-of-line (BEOL) multilayer metal lines, which is an essential 2.5D packaging paradigm. [3][4][5] However, the large gap between the sizes of transistors and TSVs not only limits the further promotion of integration granularity and interconnection density 6 but also brings about significant RC delay and heat dissipation. 7 Monolithic three-dimensional (M3D) integration, that is, fabricating active devices with local interconnections layer by layer from a common starting substrate, provides a promising method to settle the trade-offs among the performance, density, and power dissipation.…”

Layout Dependence Stress Investigation in through Glass via Interposer Architecture Using a Submodeling Simulation Technique and a Factorial Design Approach

“…Cost and yield tradeoff of chiplet and monolithic chip integration were analyzed with possibly uncertain parameters; the results show that the overall cost of chiplet design is lower than that of the monolithic chip in five-year business planning [ 31 ]. The integrated fan-out (FO) on substrate solution was demonstrated by TSMC to achieve advanced chiplet integration; the mechanical reliability and fatigue risk of the present vehicle under temperature and humidity tests were assessed [ 32 , 33 , 34 ].…”