Influence of Poly-Si Potential on Profile Distortion   Caused by Charge Accumulation

Ogino, Satoshi; Fujiwara, Nobuo; Miyatake, Hiroshi; Yoneda, Masahiro

doi:10.1143/jjap.35.2445

Cited by 25 publications

(12 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus, a correlation between this potential difference and the notch depth is expected to exist. We note that the potential distribution in the trench region remains unchanged for open area widths greater than 5 m. Thus, the notch profile for Wϭ10 m is identical to the one obtained for Wϭ5 m. Our findings discredit the conjecture that electron accumulation at the outermost line is determined solely by the solid angle available to electrons to reach the poly-Si sidewall, 16 which predicts that the notch depth should increase continuously with the open space width.…”

Section: F Notching Dependence On the Open Area Widthsupporting

confidence: 67%

“…1,16 The notch depth depends weakly on the total poly-Si perimeter bordering the open area; a three order-of-magnitude change in the perimeter doubles the notch depth under identical etching conditions. 1 Our 2D simulation cannot be used to predict quantitatively the effect of the perimeter, unless the lines are connected through the substrate.…”

Section: G Notching In Electrically Connected Poly-si Linesmentioning

confidence: 99%

See 1 more Smart Citation

On the origin of the notching effect during etching in uniform high density plasmas

Hwang

Giapis

1997

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

245

166

View full text Add to dashboard Cite

We present a two-dimensional Monte Carlo simulation of profile evolution during the overetching step of polysilicon-on-insulator structures, which considers explicitly ͑a͒ electric field effects during the charging transient, ͑b͒ etching reactions of energetic ions impinging on the poly-Si, and ͑c͒ forward inelastic scattering effects. Realistic energy and angular distributions for ions and electrons are used in trajectory calculations through local electric fields near and in the microstructure. Transient charging of exposed insulator surfaces is found to profoundly affect local sidewall etching ͑notching͒. Ion scattering contributions are small but important in matching experimental notch profiles. The model is validated by capturing quantitatively the notch characteristics and also the effects of the line connectivity and open area width on the notch depth, which have been observed experimentally by Nozawa et al. ͓Jpn. J. Appl. Phys. 34, 2107 ͑1995͔͒. Elucidation of the mechanisms responsible for the effect facilitates the prediction of ways to minimize or eliminate notching.

show abstract

Section: F Notching Dependence On the Open Area Widthsupporting

confidence: 67%

Section: G Notching In Electrically Connected Poly-si Linesmentioning

confidence: 99%

On the origin of the notching effect during etching in uniform high density plasmas

Hwang

Giapis

1997

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

245

166

View full text Add to dashboard Cite

show abstract

“…In the same figure, the notch depth is shown to increase linearly with the substrate area exposed to the plasma, capturing the experimental results of Ogino et a. 7 (see their Fig. 1 0).d The linear relationship is expected to break down upon further increase of R, as the substrate potential decreases more slowly beyond R = 0.5.…”

supporting

confidence: 83%

The Role of the Substrate on Pattern‐Dependent Charging

Hwang

Giapis

1997

J. Electrochem. Soc.

View full text Add to dashboard Cite

Monte Carlo simulations of charging and profile evolution during plasma etching reveal that the substrate can mediate current imbalance across the wafer. This function couples patterned areas, where the electron shading effect dominates, to substrate areas directly exposed to the plasma. When a net positive current flows through the pattern features to the substrate, increasing the exposed area decreases the substrate potential, thereby causing notching at the connected feature sidewalls to worsen, in agreement with experimental observations. When plasma-etching patterned wafers, the sheath-induced directionality difference between ions and electrons at the wafer causes differential microstructure charging,1 which affects the current balance at the bottom of trenches, can lead to profile distortion (notching),23 and may induce electron tunneling through thin gate oxides.14 Charging damage ensues when large tunneling currents cause electrical degradation or even breakdown of the oxide.5 The magnitude and direction of the tunneling current depends critically on the substrate potential.14 When exposed to the plasma, the substrate, even when lightly doped, can provide a path to plasma electrons to reach patterned areas from below, change the potentials of features connected to it, and thereby influence the in-trench ion dynamics. Since the substrate connects electrically all chips on a wafer, it can profoundly influence charging damage, especially in the presence of plasma nonuniformities or variations in the pattern geometry. The confusion surrounding charging effects6 has thus far prevented understanding of the role of the substrate in mediating current balance across the wafer.Often in real processing, a wafer has an Si02 layer on its back side that wraps over to the front edge;6 then, electrical contact of the substrate with the plasma can occur only through patterned areas or places where the oxide has been removed. Any current imbalance at a patterned area, where polysilicon or metal gates are connected to the substrate directly or through thin (< 10 nm) oxide, influences the substrate potential, thus affecting the current balance at other patterned regions or exposed areas. This possibility was recognized early on by Hashimoto1 and was investigated more thoroughly by Ogino et al.76 The latter used special line-andspace (L&S) structures of masked polysilicon gates, electrically connected to the substrate through a narrow via underneath. Notch occurrence was used as an indication of the gate and substrate potentials. A key result of this study was a linear increase in notch depth with exposed substrate area. It was suggested that more plasma electrons entering through the larger exposed area were able to reach the gates, decrease their potential, perturb the intrench ion dynamics, and cause the notch to deepen. Although these suggestions provide a reasonable interpretation of the experimental results, they remain heuristic. In this article, we attempt to quantify the role of the substrate potential on ...

show abstract

“…Moreover, this high-density plasma can cause profile distortion such as local side etch during polysilicon etching on a dielectric film such as gate silicon dioxide. Many studies regarding this profile distortion have been reported, and the charge-up of patterns, called the electron shading effect, is suggested as the model of the local side etch [9,10]. Depending on the plasma state and parameters, many problems arise.…”

Section: Introductionmentioning

confidence: 99%