The Role of the Substrate on Pattern‐Dependent Charging

Abstract

Monte Carlo simulations of charging and profile evolution during plasma etching reveal that the substrate can mediate current imbalance across the wafer. This function couples patterned areas, where the electron shading effect dominates, to substrate areas directly exposed to the plasma. When a net positive current flows through the pattern features to the substrate, increasing the exposed area decreases the substrate potential, thereby causing notching at the connected feature sidewalls to worsen, in agreement with experimental observations. When plasma-etching patterned wafers, the sheath-induced directionality difference between ions and electrons at the wafer causes differential microstructure charging,1 which affects the current balance at the bottom of trenches, can lead to profile distortion (notching),23 and may induce electron tunneling through thin gate oxides.14 Charging damage ensues when large tunneling currents cause electrical degradation or even breakdown of the oxide.5 The magnitude and direction of the tunneling current depends critically on the substrate potential.14 When exposed to the plasma, the substrate, even when lightly doped, can provide a path to plasma electrons to reach patterned areas from below, change the potentials of features connected to it, and thereby influence the in-trench ion dynamics. Since the substrate connects electrically all chips on a wafer, it can profoundly influence charging damage, especially in the presence of plasma nonuniformities or variations in the pattern geometry. The confusion surrounding charging effects6 has thus far prevented understanding of the role of the substrate in mediating current balance across the wafer.Often in real processing, a wafer has an Si02 layer on its back side that wraps over to the front edge;6 then, electrical contact of the substrate with the plasma can occur only through patterned areas or places where the oxide has been removed. Any current imbalance at a patterned area, where polysilicon or metal gates are connected to the substrate directly or through thin (< 10 nm) oxide, influences the substrate potential, thus affecting the current balance at other patterned regions or exposed areas. This possibility was recognized early on by Hashimoto1 and was investigated more thoroughly by Ogino et al.76 The latter used special line-andspace (L&S) structures of masked polysilicon gates, electrically connected to the substrate through a narrow via underneath. Notch occurrence was used as an indication of the gate and substrate potentials. A key result of this study was a linear increase in notch depth with exposed substrate area. It was suggested that more plasma electrons entering through the larger exposed area were able to reach the gates, decrease their potential, perturb the intrench ion dynamics, and cause the notch to deepen. Although these suggestions provide a reasonable interpretation of the experimental results, they remain heuristic. In this article, we attempt to quantify the role of the substrate potential on ...