Incremental physical resynthesis for timing optimization

Abstract

This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and physical optimizations without incurring unmanageable runtime complexity. Unlike previous approaches to this problem which limit the types of operations and/or architectural features, we take advantage of many architectural characteristics of modern FPGA devices, and utilize many types of optimizations including cell repacking, signal rerouting, resource retargeting, and logic restructuring, accompanied by efficient incremental placement, to gradually transform a design via a series of localized logic and physical optimizations that verifiably improve overall compliance with timing constraints. This procedure works well on small and large designs, and can be administered through either an automatic optimizer, or an interactive user interface. Our preliminary experiments showed that this approach is very effective in fixing or reducing timing violations that cannot be reduced by other optimization techniques: For a set of test cases to which this is applicable, the worst timing violation is reduced by an average of 42.8%.

Replace: An incremental placement algorithm for field programmable gate arrays

“…FPGA-based algorithms focus on small-scale changes: they operate on individual LUTs, and evaluate each move based upon timing [10], congestion [11], or combined [9] cost functions. These LUT-at-a-time operations are costly in runtime.…”

High-throughput linked-pattern matching for intrusion detection systems

“…However, without the use of incremental place-and-route, the system would require a completely new place-and-route, or p times additional time. Certainly a lower-level incremental change controller, possibly implemented in an embedded microprocessor core as in [16], making the required changes directly within a partition without resorting to extensive re-processing (as in [27]) would be a more effective solution.…”

A framework for layout-level logic restructuring

“…Other recent work ( [12], [16], [15]) exploits logic replication and also more general restructuring via resynthesis. In [12], given a mapped network and a placement, the network is transformed into 2-input network by replacing each Kinput gate(K ≥ 3) by a balanced binary tree ( [3]).…”

“…The decomposed gates are labeled with the best arrival time and then mapped by iteratively assessing congestion costs. In [16], incremental physical resynthesis is presented. a resynthesis window is derived based on a physical timing analysis.…”