Incorporation of boron in SiGe(C) epitaxial layers grown by reduced pressure chemical vapor deposition

Hållstedt, Julius; Parent, Arnaud; Östling, Mikael; Radamson, Henry H.

doi:10.1016/j.mssp.2004.09.074

Cited by 15 publications

(10 citation statements)

References 8 publications

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“…19. With a SiH 4 + GeH 4 + B 2 H 6 chemistry, this increase was of the order of 30% only at 575 • C. 20 Let us now deal with the real and "apparent" Ge concentrations in those SiGe:B layers. By "apparent" Ge concentration, we mean the Ge content extracted by fitting (using the Takagi-Taupin dynamical diffraction theory) the experimental XRD profiles with the following assumption: boron-doped SiGe layers behave as binary SiGe alloys (and not ternary SiGeB alloys).…”

Section: Resultsmentioning

confidence: 99%

Very Low Temperature (Cyclic) Deposition / Etch of In Situ Boron-Doped SiGe Raised Sources and Drains

Hartmann

Benevent

André

et al. 2014

ECS J. Solid State Sci. Technol.

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We have developed an innovative 500°C process for the selective deposition of SiGe:B Raised Sources and Drains (RSDs). We have first of all studied on blanket Si wafers the in-situ boron doping of SiGe with Si2H6, GeH4 and B2H6. A growth rate increase by a factor higher than 4 together with a Ge concentration decrease from 45% down to 28% occurred as the diborane mass-flow increased (at 500°C, 20 Torr). Very high substitutional boron concentrations were achieved (∼5 × 1020 cm−3) in layers that were single crystalline and flat. Adding large amounts of HCl to the gaseous mixture did not yield the selectivity aimed for on SiO2-covered Si wafers, however. To that end, we have thus benchmarked various 500°C Cyclic Deposition / Etch (CDE) processes. 12 cycles CDE processes were characterized by HCl etch rates of poly-SiGe:B that were too low to be of any practical use or yielded 3 dimensional SiGe:B layers on Si(001). Straightforward Deposition / Etch (DE) processes, with the HCl selective etch of poly-SiGe:B carried out at 740 Torr (i.e. atmospheric pressure), enabled us by contrast to achieve selectivity on SiO2 while retaining single crystalline and slightly rough SiGe:B layers. Those DE processes were tested on patterned Silicon-On-Insulator substrates with gate stacks. Longer HCl etch times than the ones identified on blanket wafers were key in getting rid of poly-SiGe:B on top of dielectrics covered surfaces; rather smooth, facetted SiGe:B RSDs were obtained in the end.

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Section: Resultsmentioning

confidence: 99%

Very Low Temperature (Cyclic) Deposition / Etch of In Situ Boron-Doped SiGe Raised Sources and Drains

Hartmann

Benevent

André

et al. 2014

ECS J. Solid State Sci. Technol.

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“…Si and SiGe layers are grown by reduced pressure chemical vapor deposition (RP-CVD). This deposition technique has already been used in the literature to realize superlattices [3,11,12]. CVD offers high layer quality and makes it possible to use in situ doping.…”

Section: Si-sige Superlattice Growthmentioning

confidence: 99%

An innovating technological approach for Si–SiGe superlattice integration into thermoelectric modules

Savelli

Plissonnier

Remondière

et al. 2008

J. Micromech. Microeng.

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This paper presents the development of doped polycrystalline Si-SiGe superlattices as thermoelectric (TE) elements integrated into generators. The modules dimension is 1 cm 2 , Si and SiGe are in situ doped (n and p types) and realized by CVD (chemical vapor deposition) on a 4 inch (0 0 1) silicon wafer. Si-SiGe superlattice growth will be studied, as well as the integration into thermoelectric modules. Interest in using superlattices as TE materials will be justified by their thermal conductivity measurements. Moreover, process fabrication and different geometry designs will be presented. Finally, the first measurements realized on these modules allowed scavenging 320 mV for a temperature difference of 90 K.

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“…[4][5][6][7] For metal-oxide-semiconductor field-effect transistors ͑MOS-FETs͒, the pattern dependency issue has a large impact on the structure profile, but the other important goals to be achieved are as follows: low sheet resistance in S/D junctions, high thermal stability of the silicide layers ͑formed for low contact resistance͒, and low dopant out-diffusion from S/D to the channel region. 8 The first two requirements can be achieved by high boron doping in SiGe epilayers. Because the presence of boron compensates the compressive strain in SiGe layers, 9 a high level of both boron and germanium is necessary for such transistors.…”

mentioning

confidence: 99%

Selective Growth of B- and C-Doped SiGe Layers in Unprocessed and Recessed Si Openings for p-type Metal-Oxide-Semiconductor Field-Effect Transistors Application

Kolahdouz

Adibi

Farniya

et al. 2010

J. Electrochem. Soc.

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This work presents the pattern dependency of the selective epitaxial growth of boron- and carbon-doped SiGe layers in recessed and unprocessed openings. The layer profile is dependent on deposition time, chip layout, and growth parameters. Carbon and boron doping compensates for the strain in SiGe layers, and when both dopants are introduced, the strain reduction is additive. The incorporation of boron and carbon in the SiGe matrix is a competitive action. The concentration of carbon decreases, whereas the boron amount increases in SiGe layers with higher Ge content. In recessed openings, the Ge content is independent of the recess depth. The strain amount in the grown layers is graded vertically, which is due to the thickness of the epilayer exceeding the critical thickness

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Incorporation of boron in SiGe(C) epitaxial layers grown by reduced pressure chemical vapor deposition

Cited by 15 publications

References 8 publications

Very Low Temperature (Cyclic) Deposition / Etch of In Situ Boron-Doped SiGe Raised Sources and Drains

Very Low Temperature (Cyclic) Deposition / Etch of In Situ Boron-Doped SiGe Raised Sources and Drains

An innovating technological approach for Si–SiGe superlattice integration into thermoelectric modules

Selective Growth of B- and C-Doped SiGe Layers in Unprocessed and Recessed Si Openings for p-type Metal-Oxide-Semiconductor Field-Effect Transistors Application

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