Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015 2015
DOI: 10.7873/date.2015.1055
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In-Place Memory Mapping Approach for Optimized Parallel Hardware Interleaver Architectures

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Cited by 7 publications
(4 citation statements)
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“…A number of application parameters allows to manage intra and inter-standards (frame size, code structure, speed). 2) In [27] and [28], authors present programmable architectures to support several and distinct ECC families. They exploit multi-standards applications scenarios.…”
Section: Related Workmentioning
confidence: 99%
“…A number of application parameters allows to manage intra and inter-standards (frame size, code structure, speed). 2) In [27] and [28], authors present programmable architectures to support several and distinct ECC families. They exploit multi-standards applications scenarios.…”
Section: Related Workmentioning
confidence: 99%
“…In few words, this means that if in the QPP interleaver any two data are accessed at the same cycle, they cannot be stored in the same memory bank in the memory mapping generated with TMap constraint. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 Then, a Constraint Graph CG taking into account all these constraints is defined and a constraint solver (from [22]) is applied (see Figure 13). If we apply this memory mapping approach the resulting memory mapping is:…”
Section: Proposed Memory Mapping Approachmentioning
confidence: 99%
“…-Bank 0 = {0, 2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,33,35,37,39,41,43,45,47,49,51,53,55,57,59, 61, 63} -Bank 1 = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62} This approach is able to generate conflict free memory mapping with respect to the output bit sequence of the inverse RM module and the QPP interleaver input order ( Figure 11). The resulting architecture does not need any additional memories (see Figure 1), since we are able to find no-conflict memory mapping in any case.…”
Section: Proposed Memory Mapping Approachmentioning
confidence: 99%
“…Designing efficient parallel hardware architecture (i.e., with no access conflicts in memory nor in the interconnection network) is a very complex and time consuming task. Several approaches have been proposed in state of the art in order to solve such "collision problem" in ECC architectures ( [19] [24][8] [23] [14][26] [15]. .…”
Section: Introductionmentioning
confidence: 99%