Solving Memory Access Conflicts in LTE-4G Standard

Lozachmeur, F.; Barguil, T.; Hussein, Assem; Coussy, Philippe

doi:10.1109/icassp.2019.8682287

Cited by 2 publications

(2 citation statements)

References 13 publications

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“…Error correction code (such Turbo and LDPC codes) can improve the reliability of signal transmission and improve the transmission quality of communication system. However, error-correcting codes have high computational complexity and irregular memory accesses [55], [56]. In order to lower hardware costs and accommodate numerous error correction codes (Turbo, LDPC, Polar codes, etc.)…”

Section: Communicationmentioning

confidence: 99%

RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions. Nowadays, RISC-V is a popular ISA for embedded processors. However, there is still a gap between the capabilities of RISC-V and the requirements of various emerging computing scenarios (e.g., artificial intelligence, cloud computing). Recently, the RISC-V standards organization has continuously introduced new ISA extensions to meet the needs of advanced computing. There are also a variety of novel research proposed customized extensions of RISC-V for certain scenarios. As far as we know, there is a lack of a survey to systematically present the research progress of RISC-V ISA extensions. The goal of this paper is to provide a comprehensive survey on existing works about RISC-V ISA extensions. First, the application scenarios of RISC-V are introduced, and the requirements for ISA extensions are analyzed. Then, we survey the progress of official RISC-V ISA extension specification and recent research on RISC-V ISA extension. Finally, we highlight some possible future research opportunities on the RISC-V ISA extension.INDEX TERMS RISC-V, instruction set architecture, extensions, survey.

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Section: Communicationmentioning

confidence: 99%

RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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“…Error-correcting codes are well-known for their high computational complexity and irregular memory accesses [29], [30]. The improvement of both efficiency and flexibility have been the subject of a continuous effort for decades.…”

Section: Ecc Decoding Algorithmsmentioning

confidence: 99%

Extended RISC-V hardware architecture for future digital communication systems

Tourres

Gal

Crenne

et al. 2021

2021 IEEE 4th 5G World Forum (5GWF)

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HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

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Solving Memory Access Conflicts in LTE-4G Standard

Cited by 2 publications

References 13 publications

RISC-V Instruction Set Architecture Extensions: A Survey

RISC-V Instruction Set Architecture Extensions: A Survey

Extended RISC-V hardware architecture for future digital communication systems

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