In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization

Abstract

Low-noise amplifiers (LNAs) play a significant role in modern millimeter-wave (mmWave) integrated circuits for fifth-generation (5G) communications systems. However, the proper analysis of their design tradeoffs that allow for a realistic topology comparison is impractical. The many conflicting specifications that must be carefully balanced make the problem intractable. In this paper, the 148dimensional performance spaces of three 28-GHz LNAs are fully explored for a 65-nm CMOS technology node, using an enhanced electronic design automation tool. One-and two-step many-objective optimizations provide up to 1024 different LNAs for each of the considered topologies, enabling a thorough assessment of their performance tradeoffs. The first optimizes all the design parameters at once. In contrast, the latter optimizes the spiral inductors in a first step. Then, in a second step, it optimizes the remaining parameters. The resulting designs provide new insight on the tradeoffs between gain, noise figure, power, and circuit's footprint for current 5G specifications. Process, voltage, and temperature corners impact the LNAs' performance severely. Still, the optimization shows that proper sizing of these topologies compete with the most-recent mmWave LNAs and can play a role in the challenging 28-GHz band.

Fast Design Space Exploration and Multi-Objective Optimization of Wide-Band Noise-Canceling LNAs

“…At this point, the two gains A 1 and A 2 are not exactly equal due to the assumption made in (10). The gain mismatch (∆A dB ) is defined as [6] ∆A dB = 20log(…”

“…[9], a tool to analyze the noisecanceling LNA was proposed, but it invoked the simulator in the loop, suffered from low accuracy, and did not address design corners and the non-linearity. The flow in [10] presented accurate results that address design corners, but it invoked the simulator in the optimization loop, which increased the time needed for the optimization to several hours.…”

Design and analysis of 28 GHz CMOS low power LNA with 6.4 dB gain variability for 5G applications

“…Low power circuit design gets importance due to the power hungry circuit operations at the radio frequency. The power consumption of a circuit is directly proportional to the frequency of operation 1 . When a RF circuit is designed for portable battery powered devices, the reduction of power consumption gets more importance 2 .…”

“…There is a trade-off between the power consumption and gain of the LNA. 1,7 To reduce the power consumption, different methods like forward biasing, current reuse technology and folded topologies have proved great performance. 8,9 Apart from these technologies, the sleep and wakeup technology helps to reduce the active power by turning off the LNA when there is no input signal from the antenna.…”

“…The power consumption of a circuit is directly proportional to the frequency of operation. 1 When a RF circuit is designed for portable battery powered devices, the reduction of power consumption gets more importance. 2 In the receiver side, the low noise amplifier (LNA) is the first active block and it operates at the radio frequency.…”