Improving the error behavior of DRAM by exploiting its Z-channel property

Kraft, Kira; Sudarshan, Chirag; Mathew, Deepak M.; Weis, Christian; Wehn, Norbert; Jung, Matthias

doi:10.23919/date.2018.8342249

Cited by 17 publications

(29 citation statements)

References 17 publications

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“…However, one potential approach to retrieve the layout of true cells (and anti-cells) would be to initialize the DRAM with '0xFF' (or '0x00'), disable the DRAM refresh operation and read back the memory contents after a period of several hours or days, i.e., at the end of the decay process. Such an approach has indeed been successfully tested by Kraft et al [51]. In the original evaluation, three different memory regions, each located on one individual PandaBoard, had been measured, with each such memory region considered as a PUF instance.…”

Section: Evaluation Of the Original Row Hammer Pufmentioning

confidence: 99%

Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security †

et al. 2018

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Physical Unclonable Functions (PUFs) based on the retention times of the cells of a Dynamic Random Access Memory (DRAM) can be utilised for the implementation of cost-efficient and lightweight cryptographic protocols. However, as recent work has demonstrated, the times needed in order to generate their responses may prohibit their widespread usage. To address this issue, the Row Hammer PUF has been proposed by Schaller et al., which leverages the row hammer effect in DRAM modules to reduce the retention times of their cells and, therefore, significantly speed up the generation times for the responses of PUFs based on these retention times. In this work, we extend the work of Schaller et al. by presenting a run-time accessible implementation of this PUF and by further reducing the time required for the generation of its responses. Additionally, we also provide a more thorough investigation of the effects of temperature variations on the Row Hammer PUF and briefly discuss potential statistical relationships between the cells used to implement it. As our results prove, the Row Hammer PUF could potentially provide an adequate level of security for Commercial Off-The-Shelf (COTS) devices, if its dependency on temperature is mitigated, and, may therefore, be commercially adopted in the near future.

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Section: Evaluation Of the Original Row Hammer Pufmentioning

confidence: 99%

Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security †

et al. 2018

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“…Hence, we can further mitigate the retention errors in ZEM with ECC. Recently, Kraft et al [30], [31] proposed to replace the SECDED by exploiting the Z-channel with single error correction code. in [30], [31], if any code-word has more than 50% of one bits, the whole code-word would be flipped before the using the error correction code.…”

Section: Boosting Error Resilience With Eccmentioning

confidence: 99%

“…Recently, Kraft et al [30], [31] proposed to replace the SECDED by exploiting the Z-channel with single error correction code. in [30], [31], if any code-word has more than 50% of one bits, the whole code-word would be flipped before the using the error correction code. In addition, [30], [31] can provide 52 ∼ 56% zero bits on floating point 32-bit and INT8 of ResNet-50, AlexNet, and GoogleNet.…”

Section: Boosting Error Resilience With Eccmentioning

confidence: 99%

“…in [30], [31], if any code-word has more than 50% of one bits, the whole code-word would be flipped before the using the error correction code. In addition, [30], [31] can provide 52 ∼ 56% zero bits on floating point 32-bit and INT8 of ResNet-50, AlexNet, and GoogleNet. However, ZEM significantly increases the percentage of zero bits (i.e.…”

Section: Boosting Error Resilience With Eccmentioning

confidence: 99%

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ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM

Nguyen

et al. 2021

IEEE Access

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In sub-20nm technologies, DRAM cells suffer from poor retention time. With the technology scaling, this problem tends to be worse, significantly increasing refresh power of DRAM. This is more problematic in memory heavy applications such as deep learning systems, where a large amount of DRAM is required, DRAM refresh power contributes to a considerable portion of total system power. With the growth in deep learning workloads, this is set to get worse. In this work, we present a zero-cycle bit-masking (ZEM) scheme that exploits the asymmetry of retention failures, to eliminate DRAM refresh in the inference of convolution neural networks, natural language processing, and the image generation based on generative adversarial network. Through careful analysis, we derive a bit-error-rate (BER) threshold that does not affect the accuracy of inference. Our proposed architecture, along with the techniques involved, are applicable to all types of DRAMs. Our results on 16Gb devices show that ZEM can improve the performance by up to 17.31% while reducing the total energy consumed by DRAM by up to 43.03%, dependent on the type of DRAM.

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“…Traditional ECC techniques for DRAMs assume a symmetric behavior of the retention errors, i.e., the error probability for a stored 0 and 1 is identical. In [22] and [23] we presented a more accurate error model for the retention behavior that exploits the internal cell structure (the so-called true-or anticells) of a DRAM. This model is asymmetric and we could show that the channel capacity according to Shannon's capacity definition (the memory cell is considered as a noisy channel) of a single memory cell is larger than in the traditional commonly used symmetrical model.…”

Section: Temperature Vs Reliabilitymentioning

confidence: 99%

The Dynamic Random Access Memory Challenge in Embedded Computing Systems

Jung

Weis

Wehn

2020

A Journey of Embedded and Cyber-Physical Systems

Self Cite

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Dynamic random access memories (DRAMs) are key components in all computing systems that require large working memory. Due to the strong increase in data volume in many embedded applications, such as machine learning, image processing, autonomous systems, etc., DRAMs largely impact the overall system performance and power consumption. In many of these applications, the overall system performance is often limited by the memory bandwidth or latency and not by the computation itself. Due to the dynamic storage scheme of DRAMs and shrinking technology nodes, reliability is also a major concern in current and future DRAMs. Therefore, new challenges arise, which we will discuss in this chapter. The most important metrics, which are typically considered for DRAM subsystems (especially in the high-performance computing (HPC) domain), are bandwidth, latency, and capacity. However, in the context of embedded systems it requires to consider further metrics, such as power, temperature, reliability, safety, and security. In the following we will highlight these challenges and refer to some of our recent contributions, which tackle these challenges.

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Improving the error behavior of DRAM by exploiting its Z-channel property

Cited by 17 publications

References 17 publications

Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security †

Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security †

ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM

The Dynamic Random Access Memory Challenge in Embedded Computing Systems

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