ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM

Abstract

In sub-20nm technologies, DRAM cells suffer from poor retention time. With the technology scaling, this problem tends to be worse, significantly increasing refresh power of DRAM. This is more problematic in memory heavy applications such as deep learning systems, where a large amount of DRAM is required, DRAM refresh power contributes to a considerable portion of total system power. With the growth in deep learning workloads, this is set to get worse. In this work, we present a zero-cycle bit-masking (ZEM) scheme that exploits the asymmetry of retention failures, to eliminate DRAM refresh in the inference of convolution neural networks, natural language processing, and the image generation based on generative adversarial network. Through careful analysis, we derive a bit-error-rate (BER) threshold that does not affect the accuracy of inference. Our proposed architecture, along with the techniques involved, are applicable to all types of DRAMs. Our results on 16Gb devices show that ZEM can improve the performance by up to 17.31% while reducing the total energy consumed by DRAM by up to 43.03%, dependent on the type of DRAM.

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

“…Doing so requires using either (i) additional operations to mitigate data loss (e.g., issuing extra row activations to those cells' rows [80]) or (ii) supplementary error-mitigation mechanisms within processor (e.g., ECC [94] and/or bit-repair techniques [79,86,103]). Although both approaches can introduce new performance and energy overheads, the benefits of reducing unnecessary refresh operations outweigh the overheads introduced [56,79,80,86,89,92,94,103,104,278]. For example, Liu et al [80] project that DRAM refresh overheads cause a 187.6% increase in the energy-per access and a 63.7% system performance degradation for 64 Gib chips.…”

A Case for Transparent Reliability in DRAM Systems

“…Doing so requires either using additional refresh operations (e.g., by issuing extra row activations [77]) or using error-mitigation mechanisms within processor (e.g., ECC [82] and/or bit-repair techniques [22,76,79]). Although both strategies introduce new performance and energy overheads, the bene ts of reducing unnecessary refresh operations outweigh the overheads introduced [22,[76][77][78][79][80]82,125,126,325]. For example, Liu et al [77] project that DRAM refresh overheads cause a 187.6% increase in the energy-per access and a 63.7% system performance degradation for 64 Gib chips.…”