The Dynamic Random Access Memory Challenge in Embedded Computing Systems

Jung, Matthias; Weis, Christian; Wehn, Norbert

doi:10.1007/978-3-030-47487-4_3

Cited by 3 publications

(2 citation statements)

References 39 publications

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“…Because the processor works at a higher speed than the memory frequency, the processor demands data faster than memory can deliver it. Conversely, data from the processor are available for transfer faster than the DRAM can store them, creating bottlenecks [11]. Mobility optimization would improve this challenge (obj.…”

Section: Ee Challengesmentioning

confidence: 99%

A review of CNN accelerators for embedded systems based on RISC-V

Sanchez-Flores

Alvarez

Alorda

2022

2022 IEEE International Conference on Omni-Layer Intelligent Systems (COINS)

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One of the great challenges of computing today is sustainable energy consumption. In the deployment of edge computing this challenge is particularly important considering the use of embedded equipment with limited energy and computation resources. In those systems, the energy consumption must be carefully managed to operate for long periods. Specifically, for embedded systems with machine learning capabilities in the Internet of Things (EMLIoT) era, the convolutional neural networks (CNN) model execution is energy challenging and requires massive data. Nowadays, high workload processing is designed separately into a host processor in charge of generic functions and an accelerator dedicated to executing the specific task. Open-hardware-based designs are pushing for new levels of energy efficiency. For achieving energy efficiency, open-source tools, such as the RISC-V ISA, have been introduced to optimize every internal stage of the system. This document aims to compare the EMLIoT accelerator designs based on RISC-V and highlights open topics for research.

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Section: Ee Challengesmentioning

confidence: 99%

A review of CNN accelerators for embedded systems based on RISC-V

Sanchez-Flores

Alvarez

Alorda

2022

2022 IEEE International Conference on Omni-Layer Intelligent Systems (COINS)

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“…HBM, common in GPUs, FPGA-CPUs and System on Chips like the Xilinx UltraScale+, is better equipped to handle increased memory requirements of GPU and accelerator-based architectures [4], [5]. A recent study suggests the combination of low power consumption and high bandwidth make this category of memory ideal for embedded systems as well [6].…”

Section: Introductionmentioning

confidence: 99%

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems

Asifuzzaman

Abuelala

Hassan

et al. 2021

2021 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

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The number of functionalities controlled by software on every critical real-time product is on the rise in domains like automotive, avionics and space. To implement these advanced functionalities, software applications increasingly adopt artificial intelligence algorithms that manage massive amounts of data transmitted from various sensors. This translates into unprecedented memory performance requirements in critical systems that the commonly used DRAM memories struggle to provide. High-Bandwidth Memory (HBM) can satisfy these requirements offering high bandwidth, low power and high-integration capacity features. However, it remains unclear whether the predictability and isolation properties of HBM are compatible with the requirements of critical embedded systems. In this work, we perform to our knowledge the first timing analysis of HBM. We show the unique structural and timing characteristics of HBM with respect to DRAM memories and how they can be exploited for better time predictability, with emphasis on increased isolation among tasks and reduced worst-case memory latency.

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Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure

Siddhu,

Bagchi,

Kedia

et al. 2023

ACM Trans. Embed. Comput. Syst.

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Modern high-performance and high-bandwidth 3D memories are characterized by frequent heating. Prior art suggests turning off hot channels and migrating data to the background DDR memory, incurring significant performance and energy overheads. We propose three Dynamic Thermal Management (DTM) approaches for 3D memories, reducing these overheads. The first approach, Rotating channel Low power state based DTM (RL-DTM) , minimizes the energy overheads by avoiding data migration. RL-DTM places 3D memory channels into low power states instead of turning them off. Since data accesses are disallowed during low power state, RL-DTM balances each channel’s low power state duration. The second approach, Masked rotating channel Low power state based DTM (ML-DTM) , is a fine-grained policy that minimizes the energy-delay product (EDP) and improves the performance of RL-DTM by considering the channel access rate. The third strategy, Partial channel closure and ML-DTM (PML-DTM) minimizes performance overheads of existing channel-level turn-off based policies by closing a channel only partially and integrating ML-DTM, reducing the number of channels being turned off. We evaluate the proposed DTM policies using various mixes of SPEC benchmarks and multi-threaded workloads, and observe them to significantly improve performance, energy, and EDP over state-of-the-art approaches for different 3D memory architectures.

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The Dynamic Random Access Memory Challenge in Embedded Computing Systems

Cited by 3 publications

References 39 publications

A review of CNN accelerators for embedded systems based on RISC-V

A review of CNN accelerators for embedded systems based on RISC-V

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems

Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure

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