Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design

Di, Jia; Yuan, J.S.; DeMara, Ronald F.

doi:10.1016/j.vlsi.2004.08.002

Cited by 6 publications

(7 citation statements)

References 11 publications

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“…In Pipeline gating technique [6,7] , clock gating used in Data path direction in the pipeline. The system clock is distributed to the different sections as a sub clock based on the precision of the input data.…”

Section: Pipeline Gating Techniquementioning

confidence: 99%

“…The polarity inversion Technique [3] not taken care of sign extension problem in multipliers. The pipe line gating technique disabling the stages only in the direction of data flow [6] , also this cannot be directly applied for the pipelined system, because the latency is not fixed. For implementing the pipeline concept, latency must be known and fixed.…”

Section: Problem Descriptionmentioning

confidence: 99%

“…Though many efforts have been focused on the improvement of multiplier designs [1,3,4,6,7] to challenge the high speed circuit is the high power consumption, which is not a tolerable price to pay in recent mobile technologies. Digital multipliers are the most critical arithmetic functional unit in many DSP applications, e.g., Fourier Transform, DCT, filtering, etc., Array and parallel multipliers are very welcomed due to their high execution speed and throughput.…”

Section: Introductionmentioning

confidence: 99%

“…This method not taken care of power dissipation due to unwanted transitions due to sign extension problem so that the multiplicands in lower precision still cannot be processed directly. A clock gating method [6] is used to design a reconfigurable multiplier. In this method pipeline stages are selectively disabled by gating clocks and to select correct results by multiplexers.…”

Section: Introductionmentioning

confidence: 99%

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FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating

Senthilkumar¹,

Natarajan²

2008

J. of Computer Science

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With the emergence of portable computing and communication system, power awareness is one of the major objectives of VLSI Design. This is its ability to scale power consumption based on the time-varying nature of inputs. Even though the system is not designed for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are more power aware than others. Equivalently, the system should be able to re designed to increase their power awareness. This research proposes a pipelined Variable precision gating scheme to improve the power awareness of the system. This research illustrates this technique by applying it to FPGA Implementation of multipliers and digital FIR filters. This proposed technique is to clock gating to registers in both data flow direction and vertical to data flow direction within the individual pipeline stage based on the input data precision. For signed multipliers using 2's complement representation, sign extension, which wastes power and causes longer delay, could be avoided by implementing this technique. Very little additional area is needed for this technique. The designed circuit is simulated, synthesized and implemented in Xilinx Spartan 3e FPGA. The Power is analyzed for the designed circuit and the power saving of 18 % obtained for the proposed FIR Filter with 3 % increase in area compared to the existing pipeline gating design

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Section: Pipeline Gating Techniquementioning

confidence: 99%

Section: Problem Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating

Senthilkumar¹,

Natarajan²

2008

J. of Computer Science

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“…Baugh Wooley Multiplier 35 is used for 2's complement multiplication. It adjusts the partial products to maximize regularity of the multiplication array.…”

Section: Baugh Wooley Multipliermentioning

confidence: 99%

Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks

Kudithipudi¹,

John²

2005

Journal of Low Power Electronics

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The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization and optimization of such low power multipliers will aid in comparison and choice of multiplier modules in system design. In this paper we performed a comparative analysis of the power, delay, and power delay product (PDP) optimization characteristics of four parallel digital multipliers implemented using low power 10 transistor (10T) adders and conventional CMOS adder cells. In order to achieve optimal power savings at smaller geometry sizes, we proposed a heuristic approach known as hybrid adder models. Multipliers realized using the Static Energy Recovery Full adder (SERF) circuit consumed considerably less power compared to 10T and static CMOS based multipliers for all the configurations studied. Furthermore, the difference between the power consumption of the 10 transistor based multipliers and 28T multipliers is significant at 180 nm, but not at 70 nm. For smaller geometry sizes down to 70 nm, the propagation delay of the multipliers implemented with 10 transistors translates to a better performance measure. Carry-Save Multipliers had better PDP range than the other multipliers for all the three adder sub-module designs. The PDP measure for optimal scaled gate width resulted in a best-case scenario for SERF Wallace tree multiplier as compared to the other three SERF based multipliers. This can be attributed to the fast computational capability of the Wallace Tree multiplier and SERF adders' recovery energy logic saving more power at deep sub-micron sizes. The proposed SERF-10T Hybrid adder model multipliers consumed the least power of all the Hybrid and regular models with no deterioration in performance. Taken together, these results suggest that SERF-10T Hybrid model based multipliers are suited for ultra low power design and fast computation at smaller geometry sizes.

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An unsigned truncated sequential multiplier with variable error compensation

Tabei

Nikmehr

2017

Microprocessors and Microsystems

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Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design

Cited by 6 publications

References 11 publications

FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating

FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating

Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks

An unsigned truncated sequential multiplier with variable error compensation

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