FPGA Implementation of Power Aware FIR Filter Using Reduced Transition Pipelined Variable Precision Gating

Abstract

With the emergence of portable computing and communication system, power awareness is one of the major objectives of VLSI Design. This is its ability to scale power consumption based on the time-varying nature of inputs. Even though the system is not designed for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are more power aware than others. Equivalently, the system should be able to re designed to increase their power awareness. This research proposes a pipelined Variable precision gating scheme to improve the power awareness of the system. This research illustrates this technique by applying it to FPGA Implementation of multipliers and digital FIR filters. This proposed technique is to clock gating to registers in both data flow direction and vertical to data flow direction within the individual pipeline stage based on the input data precision. For signed multipliers using 2's complement representation, sign extension, which wastes power and causes longer delay, could be avoided by implementing this technique. Very little additional area is needed for this technique. The designed circuit is simulated, synthesized and implemented in Xilinx Spartan 3e FPGA. The Power is analyzed for the designed circuit and the power saving of 18 % obtained for the proposed FIR Filter with 3 % increase in area compared to the existing pipeline gating design

Software-based Control Algorithm for Providing Convergence Region with an Increasing Polynomial under Windowed FIR Filters

“…Accordingly, criterion when choosing the reconstitution frequency can be determined by using the Nyquist-Shannon theorem, where the sampling frequency is at least twice the fundamental frequency of the discrete-time signal. In practical terms, due to the sampling time (Senthilkum and Natarajan, 2008), a frequency that extrapolates the fundamental frequency of the signal is often applied, thus generating points between smaller intervals and ensuring a reliable reconstitution (Burrus and Parks, 1970).…”

High performance and low‐power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA

“…First category, uses pipelining and parallel processing techniques to increase operational frequency. This method is used in [4][5][6]. The second category includes designs which select better and high-speed multipliers and adders for implementation, low-power and high-speed FIR filters, for example, booth multipliers, array multipliers, Wallace tree adders, serial multipliers and adders and so on.…”

“…As seen in the figure, power consumption is low in comparison with other works. Table 4 shows power consumption in the proposed method and in [6,15]. In [6], target FPGA is Spartan 3E and the number of bits are eight also in [15], target FPGA is Spartan 3E and the number of bits are 16.…”

“…A multiplierless technique, based on add and shift method and common subexpression elimination for, low‐power and high‐speed FIR filters. Senthilkumar and Natarajan [6] proposed a pipelined variable precision gating scheme to improve the power awareness of the system. Another technique is clock gating to registers in both data flow direction and vertical to the data flow direction within the individual pipeline stage based on input data precision.…”

Low Power FPGA Implementation of Digital FIR Filter Based on Low Power Multiplexer Base Shift/Add Multiplier

“…This technique is used on adders, booth multipliers. In [6] this research proposes a pipelined variable precision gating scheme to improve the power awareness of the system. This research illustrates this technique is to clock gating to registers in both data flow direction and vertical to data flow direction within the individual pipeline stage based on the input data precision.…”