High performance and low‐power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA

Rashidi, Bahram

doi:10.1049/iet-spr.2013.0153

Cited by 14 publications

(7 citation statements)

References 7 publications

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“…The proposed design possesses 31.7% and 63.3% improvement in the normalized SDP than DA-based FIR filter [12] and Xilinx FIR compiler [27] respectively while implemented on Virtex-5 FPGA device. Comparisons of the implementation results on Virtex-4 FPGA device with those of [8] reveal 57% improvement for the proposed VHBCSE algorithm. (9) To show the efficiency of the proposed design in terms of power consumption on Xilinx XCV2000E FPGA platform, three linear phases FIR filters comprising 16-Tap, 32-Tap, and 64-Tap have been designed by using VHBCSE algorithm based constant multiplier.…”

Section: Hardware Implementation Results and Discussionmentioning

confidence: 85%

“…Step: In the proposed VHBCSE algorithm based constant multiplier the adder step can be defined as (8) where the term is due to the 2-bit BCS and the term is due to the fact that the word-length for the coefficients has been considered of 16 bits. Table I shows the summary of hardware complexities and the propagation delays required for the proposed VHBCSE, 2-bit BCSE [14] and 3-bit BCSE algorithms [13].…”

Section: Complexity Analysis Of Vhbscementioning

confidence: 99%

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An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

Hatai

Chakrabarti

Banerjee

2015

IEEE Trans. Circuits Syst. I

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The Power is the main challenging factor in very large scale integrated circuits. Transpose form fir filters produce better results compared to the direct form FIR filters for reconfigurable applications. In the existing method, the possibility of realization of FIR filter in transpose form configuration Using Common Sub expression Elimination was explored.. This paper explains comparison of two different architectures for low complexity FIR filters namely Constant shift method (CSM), programmable shift methods (PSM) and vertical-horizontal binary common sub-expression elimination (VHBCSE). The FIR filters can efficiently implemented by using constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) instead of common sub-expression elimination (CSE). This technique is capable of reducing the average probability of using the switching activity of the multiplier block adders compared to that of existing algorithm i.e., Binary Common sub-expression elimination (BCSE) algorithm. The filter architecture is capable of operating for word length filter coefficient without any overhead in the hardware circuitry. This VHBCSE produce the better power results. Keywords: Constant shift method (CSM), Programmable shift method (PSM), Vertical-Horizontal Binary Common Sub-expression Elimination (VHBCSE), and Binary common sub-expression elimination (BCSE.) I. INTRODUCTION FINITE-IMPULSE response (FIR) digital filter plays an important role in digital signal processing applications, such as speech processing, loud speaker equalization, echo cancellation, adaptive noise cancellation, and various communication applications, including software-defined radio (SDR) and so on. These applications require FIR filters of large order to meet the frequency specifications. These filters need to support high sampling rate for very high-speed digital communication. The number of multiplications and additions required for each filter output, increases linearly with the filter order. Since there is no redundant computation available in the FIR filter algorithm, real-time implementation of a large order FIR filter in a resource contained environment is daunting and challenging task.

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Section: Hardware Implementation Results and Discussionmentioning

confidence: 85%

Section: Complexity Analysis Of Vhbscementioning

confidence: 99%

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

Hatai

Chakrabarti

Banerjee

2015

IEEE Trans. Circuits Syst. I

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“…1 and 2) require less hardware complexity as well as less power consumption as compared with the conventional implementation approaches. Table 7 reports the comparison of hardware utilisation of the proposed work with other reported works in the light of the results reported in [33].…”

Section: Resultsmentioning

confidence: 99%

Modified artificial bee colony optimisation based FIR filter design with experimental validation using field‐programmable gate array

Dwivedi

Ghosh

Londhe

2016

IET signal process.

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Optimisation based design of finite impulse response (FIR) filters has been an active area of research for quite some time. The various algorithms proposed for FIR filter design aim at meeting a set of desired specifications in the frequency domain. Evolutionary algorithms have been found to be very effective for FIR filter design because of the non‐linear, non‐differentiable and non‐convex nature of the associated optimisation problem. The present work proposes two modified versions of a recently developed evolutionary technique i.e. artificial bee colony (ABC) algorithm for design of FIR filters. The applicability of the proposed approach has been evaluated by comparing its response with conventional reported filter design techniques. The proposed variants of ABC are found to outperform other non‐convex algorithms in achieving the desired specifications. In addition to the simulation results, the designed filters have been implemented in hardware using Xilinx‐xc7vx330t‐3ffg1157 (Virtex‐7) field programmable gate array. The hardware implementation allows validation of the proposed techniques for practical filtering applications by considering real time operation parameters.

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“…In this table, value of LUT, slice register, Bonded IOB, and power consumption are presented for different Virtex devices. The existing multiplier such as Modified Retiming Serial Multiplier (MRSM) [10], Digit Based Montgomery Multiplier (DBMM) [12], Fast parallel Decimal Multiplier (FPDM) [20] and WTM-NA are implemented in different FPGA devices such as Virtex 4, Virtex 6, Virtex 7, and Zync-7000. In MRSM [10], Finite Impulse Response (FIR) filter based ring topology was designed which contained adders and multipliers.…”

Section: Fpga Synthesismentioning

confidence: 99%

“…The existing multipliers are high-speed Baugh Wooley [6], Baugh Wooley with unsigned [7], approximate multiplier with carry predictor [8], energy-efficient approximate multiplier [9], modified retiming serial multiplier [10], fast multiplier [11], Montgomery multiplier [12], array multiplier [13], etc. These multipliers require more power and area for performing the multiplication.…”

Section: Introductionmentioning

confidence: 99%

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

Monica¹,

Anuradha²,

Syed³

et al. 2021

IJIES

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Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

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High performance and low‐power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA

Cited by 14 publications

References 7 publications

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

Modified artificial bee colony optimisation based FIR filter design with experimental validation using field‐programmable gate array

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

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