Improving Network-on-Chip-based Turbo Decoder Architectures

Abstract

In this work novel results concerning Network-on-Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidthreduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support doublebinary codes, by exploiting bit-level and pseudo-floating-point representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40% with a performance degradation of about 0.2 dB.

A Network-on-Chip-based turbo/LDPC decoder architecture

“…Since the turbo code used in the WiMAX standard is double-binary each message λ i,j is a vector of three elements. According to [23], sending bit-level (BL) instead of symbol-level extrinsic information reduces the NoC complexity of roughly 1/3. Resorting to the solution proposed in [24] this complexity reduction comes at the expense of a 0. for each of the 3 windows assigned to every one of the 22 SISOs.…”