A Network-on-Chip-based turbo/LDPC decoder architecture

Abstract

The current convergence process in wireless technologies demands for strong efforts in the conceiving of highly flexible and interoperable equipments. This contribution focuses on one of the most important baseband processing units in wireless receivers, the forward error correction unit, and proposes a Network-on-Chip (NoC) based approach to the design of multi-standard decoders. High level modeling is exploited to drive the NoC optimization for a given set of both turbo and Low-Density-Parity-Check (LDPC) codes to be supported. Moreover, synthesis results prove that the proposed approach can offer a fully compliant WiMAX decoder, supporting the whole set of turbo and LDPC codes with higher throughput and an occupied area comparable or lower than previously reported flexible implementations. In particular, the mentioned design case achieves a worst-case throughput higher than 70 Mb/s at the area cost of 3.17 mm 2 on a 90 nm CMOS technology.

Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders

“…However, as soon as Table 1 it is possible to make some important observations. As expected from previous analysis [13,27] Table 1. The choice of the threshold is not very critical, as shown by curves labeled as "Similar THR" in Fig.…”

Advanced Hardware Design for Error Correcting Codes

“…Using these codes only minor modifications are required for the check nodes and the routing network to support all codes of the IEEE 802.11ad family. For a more detailed explanation of the CN splitting scheme see [47]. A similar scheme as proposed there can also be applied on the unrolled architecture.…”

“…Several flexible on-chip interconnection networks have been proposed with the aim of fully exploiting the parallelism of the LDPC/turbo decoder architecture by reducing the message latency, alleviating the memory conflicts and efficiently routing any permutation law. Among the recent related contributions we can cite the work presented in [46] which proposes a NoC architecture based on binary de Bruijn topology and the work presented in [47] which proposes a NoCbased multiprocessor architecture, based on generalized Kautz topology.…”

A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi - core Processor

“…In this paper, a NOC multi-core processor is designed. Being different with [4], by using a message-passing programming model, the proposed NOC processor has low complexity in hardware and high flexibility of software which gives the programmer more freedom to realize the parallelized turbo decoding algorithm. The software radio approach makes the system easy to transplant and update.…”