Investigation of turbo decoding techniques based on lottery arbiter in 3D network on chip

Suaganthy, M.; Karthikeyan, A.; Kuppusamy, P. G.

doi:10.1016/j.micpro.2019.102885

Cited by 5 publications

(1 citation statement)

References 9 publications

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“…The introduction of smart devices in almost every sphere of life demands high throughput capabilities. The data rates have increased from several kilobytes/sec to almost several mega-bytes/sec (Suaganthy et al, 2019). As a result, implementation of a NoC that can handle such high data rate becomes one of the preferred design choices.…”

Section: Introductionmentioning

confidence: 99%

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

Khan

Mir

Din

2021

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Purpose This work focused on a basic building block of an allocation unit that carries out the critical job of deciding between the conflicting requests, i.e. an arbiter unit. The purpose of this work is to implement an improved hybrid arbiter while harnessing the basic advantages of a matrix arbiter. Design/methodology/approach The basic approach of the design methodology involves the extraction of traffic information from buffer signals of each port. As the traffic arrives in the buffer of respective ports, information from these buffers acts as a source of differentiation between the ports receiving low traffic rates and ports receiving high traffic rates. A logic circuit is devised that enables an arbiter to dynamically assign priorities to different ports based on the information from buffers. For implementation and verification of the proposed design, a two-stage approach was used. Stage I comprises comparing the proposed arbiter with other arbiters in the literature using Vivado integrated design environment platform. Stage II demonstrates the implementation of the proposed design in Cadence design environment for application-specific integrated chip level implementation. By using such a strategy, this study aims to have a special focus on the feasibility of the design for very large-scale integration implementation. Findings According to the simulation results, the proposed hybrid arbiter maintains the advantage of a basic matrix arbiter and also possesses the additional feature of fault-tolerant traffic awareness. These features for a hybrid arbiter are achieved with a 19% increase in throughput, a 1.5% decrease in delay and a 19% area increase in comparison to a conventional matrix arbiter. Originality/value This paper proposes a traffic-aware mechanism that increases the throughput of an arbiter unit with some area trade-off. The key feature of this hybrid arbiter is that it can assign priorities to the requesting ports based upon the real-time traffic requirements of each port. As a result of this, the arbiter is dynamically able to make arbitration decisions. Now because buffer information is valuable in winning the priority, the presence of a fault-tolerant policy ensures that none of the priority is assigned falsely to a requesting port. By this, wastage of arbitration cycles is avoided and an increase in throughput is also achieved.

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Section: Introductionmentioning

confidence: 99%