Improving breakdown performance for SOI LDMOS with sidewall field plate

Abstract

In this work, a silicon-on-insulator (SOI) lateral diffused MOSFET (LDMOS) incorporated with sidewall field plate (SEP) is presented and investigated using three-dimensional numeric simulation. A new additional electric field peak is formed, due to the compound field plate established along the n-drift region. The lateral surface electric field can be modulated, which enhances the breakdown voltage. Meanwhile, the doping concentration of n-drift region is increased, which decreases the specific on-resistance. Compared with the superjunction LDMOS, a 23.7% increase in the breakdown voltage and a 21.7% decrease in the specific on-resistance are obtained in the SFP-LDMOS device.

A super-junction SOI-LDMOS with low resistance electron channel

“…The Table 1 shows the main performance parameters of LDMOS with the experimental and simulated data reported previously in Refs. [9,16,18]. The FOM (Baliga's figure of merit) is defined as BV 2 /R on,sp to describe the trade-off performance of the devices.…”

“…It can not only effectively reduce the R on,sp but also increase the BV, and the FOM is significantly improved. [12][13][14][15][16][17][18] In the design of LD-MOS, SJ is used in many structures. For example, the BSD-SJLDMOS proposed by Duan Baoxing et al [19] And, MFBL-SJLDMOS proposed by Cao et al [20] In addition, We realize the structure with lateral width variation using super-junction technology and call it VLW-LDMOS.…”

Deep neural network-based approach for breakdown voltage and specific on-resistance prediction of SOI LDMOS with field plate

“…4,5) Hence, to modify the electric field distribution, field plate technology has been developed. [6][7][8][9][10] Nowadays, for practical devices, this technology has become an essential part. At the same time, the analysis of BV and R on,sp of the device becomes more complicated due to the introduction of the field plate.…”