A reverse-conducting lateral insulated-gate bipolar transistor (RC-LIGBT) with a trench oxide layer (TOL), featuring a vertical N-buffer and P-collector is proposed. Firstly, the TOL enhances both of the surface and bulk electric fields of the N-drift region, thus the breakdown voltage (BV) is improved. Secondly, the vertical N-buffer layer increases the voltage drop V PN of the P-collector/N-buffer junction, thus the snapback is suppressed. Thirdly, the P-body and the vertical N-buffer act as the anode and the cathode, respectively, to conduct the reverse current, thus the inner diode is integrated. As shown by the simulation results, the proposed RC-LIGBT exhibits trapezoidal electric field distribution with BV of 342.4 V, which is increased by nearly 340% compared to the conventional RC-LIGBT with triangular electric fields of 100.2 V. Moreover, the snapback is eliminated by the vertical N-buffer layer design, thus the reliability of the device is improved.
A RC-LIGBT with separated LDMOS and LIGBT by the Lshaped SiO 2 layer is proposed and investigated. The L-shaped SiO 2 layer enhances the bulk electric field remarkably and decreases the surface electric field substantially in the breakdown state. At the forward conduction, the current is dominated by the unipolar mode (LDMOS) before point A and bipolar mode (LIGBT) after point B, the snapback is eliminated between point A and B due to the conductivity modulation is restricted at the LIGBT region. The Free-Wheeling diode (FWD) is realized by the LDMOS region at reverse conduction state. Compared with the conventional RC-LIGBT, the proposed device shows snapbackfree property and it increases the BV by 107% at the same time.
MOSFETs and MOS capacitors (MOSCAPs) have been fabricated on Si-face of 4H-SiC to investigate the negative bias temperature instability (NBTI) characteristics of SiC MOSFETs. The shifts of threshold voltage of MOSFETs ranged from -216mV to -1257mV after stressed by 1000sec of -1V to -15V gate bias, correspondingly. The negative shift of the threshold voltage indicated that there were positive charges piled up at or near the oxide/SiC interface. In the mean time, the flat-band voltage shifts of SiC MOSCAPs using the same oxide after stressed by -15V bias for 28800 sec at 175°C were negligible, due to insufficient supply of holes, thus suggesting that the NBTI observed in this study was primarily participated by hole trapping, instead of electron emission. The time evolution of DVth induced by negative bias stress was found to saturate quickly, also suggesting that positive charges were primarily coming from trapping of pre-existing near-interface oxide traps, instead of generation of interface traps. The DVth induced by negative bias stress was lower at higher temperature which might be attributed to faster recovery of hole trapping at elevated temperature.
A novel shorted anode lateral-insulated gate bipolar transistor (SA LIGBT) with snapback-free characteristic is proposed and investigated. The device features a controlled barrier V barrier and resistance R SA in anode, named CBR LIGBT. The electron barrier is formed by the P-float/N-buffer junction, while the anode resistance includes the polysilicon layer and N-float. At forward conduction stage, the V barrier and R SA can be increased by adjusting the doping of the P-float and polysilicon layer, respectively, which can suppress the unipolar mode to eliminate the snapback. At turn-off stage, the low-resistance extraction path (N-buffer/P-float/polysilicon layer/N-float) can quickly extract the electrons in the N-drift, which can effectively accelerate the turn-off speed of the device. The simulation results show that at the same V on of 1.3 V, the E off of the CBR LIGBT is reduced by 85%, 73%, and 59.6% compared with the SSA LIGBT, conventional LIGBT, and TSA LIGBT, respectively. Additionally, at the same E off of 1.5 mJ/cm2, the CBR LIGBT achieves the lowest V on of 1.1 V compared with the other LIGBTs.
A novel Reverse Conduction Insulated Gate Bipolar Transistor (RC-IGBT) with Lateral Free-Wheeling Diode (FWD) integrated in the Termination is proposed and investigated by simulation, named LDT-RC-IGBT. Firstly, the Equi-Potential Ring (EPR) of the termination acts as an anode and the N-Stopper/N-Collector of the termination acts as the cathode of the anti-parallel built-in diode. The N-Stopper/N-Collector is shorted to the P-Collector, and it also acts as the electric filed stopper in the breakdown state. Secondly, the N-Collector and the P-Collector are designed apart at the surface and bottom, respectively. Thus the short effect of the N-Collector of the conventional RC-IGBT is avoided, and the snapback is completely eliminated. Thirdly, the P-Collector is not replaced by the N-Collector so that the hole injection is much higher than the conventional RC-IGBT, thus the forward voltage drop (V on ) can be reduced remarkably, which is favorable to the decrease of conducting energy loss. The results show that, the LDT-RC-IGBT not only eliminates the snapback but also reduces V on , it achieves a better tradeoff between V on and turn-off loss E off . At the same V on of 1.27 V, the E off of LDT-RC-IGBT is 2.06 mJ/cm 2 , which is 35.2%, 45.2% and 46.3% lower than that of the conventional RC-IGBT(3.19 mJ/cm 2 ), TPRC-IGBT(3.78 mJ/cm 2 ) and DARC-IGBT(3.85 mJ/cm 2 ), respectively. At the same E off of 3.10 mJ/cm 2 , the V on of LDT-RC-IGBT is 1.17 V, which is 10% and 15.8% lower than that of the conventional RC-IGBT(1.30 V) and the DARC-IGBT(1.39 V), respectively. RC-IGBT, breakdown voltage, turn-off, snapback. INDEX TERMS
The influences of positive fixed oxide charges and donor-like interface traps on breakdown voltages of SiC devices with FGR and JTE terminations were studied. The breakdown voltages of devices with both FGR and JTE terminations were found to degrade when the level of fixed oxide charges overs 1×1012 cm-2 due to enhancement of junction curvature by fixed oxide charges. The introduction of donor-like interface traps at the interface shows similar behaviors as fixed positive charges, suggested that both fixed oxide charges and interface traps should be taken into account when one optimizes device designs and processes.
A novel snapback-free and fast-switching Shorted-Anode Lateral Insulated Gate Transistor (SA LIGBT) with Multiple Current P-Plugs (MCP) in anode, named MCP LIGBT, is proposed and investigated. The device features Multiple separated Current P-Plugs which are inserted in the N-buffer. At the forward conduction mode, the MCP act as the potential barrier to block the electrons flowing directly to the N+ anode, and the N-channels sandwiched between the MCP are fully depleted, which both increase the anode distributed resistance (RSA). In the turn off process, the N-channels provide three high-speed paths for minorities extraction, which reduces the turn off time. Consequently, the proposed device not only eliminates the snapback effect, but also achieves superior tradeoff between Eoff and Von. At the same
The printed circuit board is rich in recyclable metals Cu, Au, Ag, Pt, Pb, etc. The precious metals such as gold are extracted from it, which is in line with the concept of resource recycling. In this paper, the theorem method was used to extract gold from waste circuit boards. The effects of reaction time, reaction temperature, theorem concentration, and Fe3 + mass concentration on gold leaching rate were investigated. The results showed that the pH was controlled at about 1, the theorem concentration was 0.12 mol/L, FeCl3 was 0.024 mol/L, the stirring speed was 300 r/min, and the leaching time was 2 h. Under the above conditions, the gold leaching rate reached 90.37 %. The theorem gold extraction method has certain potential application values due to its rapid gold dissolution, low toxicity during leaching, low price, high efficiency, and environmental protection.
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