Improvement of the Bias Stress Stability in 2D MoS2 and WS2 Transistors with a TiO2 Interfacial Layer

Abstract

The fermi-level pinning phenomenon, which occurs at the metal–semiconductor interface, not only obstructs the achievement of high-performance field effect transistors (FETs) but also results in poor long-term stability. This paper reports on the improvement in gate-bias stress stability in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs with a titanium dioxide (TiO2) interfacial layer inserted between the 2D TMDs (MoS2 or WS2) and metal electrodes. Compared to the control MoS2, the device without the TiO2 layer, the TiO2 interfacial layer deposited on 2D TMDs could lead to more effective carrier modulation by simply changing the contact metal, thereby improving the performance of the Schottky-barrier-modulated FET device. The TiO2 layer could also suppress the Fermi-level pinning phenomenon usually fixed to the metal–semiconductor interface, resulting in an improvement in transistor performance. Especially, the introduction of the TiO2 layer contributed to achieving stable device performance. Threshold voltage variation of MoS2 and WS2 FETs with the TiO2 interfacial layer was ~2 V and ~3.6 V, respectively. The theoretical result of the density function theory validated that mid-gap energy states created within the bandgap of 2D MoS2 can cause a doping effect. The simple approach of introducing a thin interfacial oxide layer offers a promising way toward the implementation of high-performance 2D TMD-based logic circuits.

Antisite defect qubits in monolayer transition metal dichalcogenides

“…Note that although the as-grown monolayer MoS 2 is usually n -type, there is strong experimental evidence that the Fermi energy in monolayer TMDs can be controlled effectively 34 , 35 . Furthermore, the Fermi level in ultrathin 2D systems can be tuned via electrostatic gating 36 . The computed formation energies for the neutral antisites are relatively high, indicating that the intrinsic concentration of antisite defects in as-grown TMDs under equilibrium conditions would be relatively low, see Supplementary Note 9 for details.…”

Preparation and Properties of 2D Materials

“…Interestingly, the low off current was attributed to the depletion region in the BP layer. Meanwhile, a TiO 2 interfacial layer inserted between a metal and 2D TMDCs (MoS 2 and WS 2 ) can also lead to enhanced FET properties [9]. In addition, a stable electrical performance could be achieved under a gate bias stress condition, since the TiO 2 interfacial layer serves as a Fermi level depinning layer, which reduces the density of the interface states.…”

Ultrathin Al‐Assisted Al2O3 Passivation Layer for High‐Stability Tungsten Diselenide Transistors and Their Ambipolar Inverter

“…[ 1–3,5,7,13–19 ] Several researches on gate bias stress test of TMD‐based transistors also have been reported. [ 20,21 ] However, most previous research on TMDs has not focused on their stability against bias and illumination stress. It is crucial to investigate the stability of TMD devices and develop a new method to improve their stability against bias and illumination stress for future practical and industrial applications.…”