Improved CMOS performance via enhanced carrier mobility

Mooney, P. M.

doi:10.1016/j.mseb.2006.06.048

Cited by 3 publications

(3 citation statements)

References 33 publications

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“…6 Controlling strain is then a challenge and its characterization both experimentally and theoretically an important advancement. 7,8 Indeed, with the continuous decrease in the size of devices, it becomes important to understand the properties of materials and boundaries at lower and lower dimensions, which requires to develop specific experimental and numerical methods. From the former point of view, recent methods like holography interferometry allow to map strain in materials at nanometric scale with high resolution.…”

Section: Introductionmentioning

confidence: 99%

Atomistic modeling of strain and diffusion at theSi/SiO2interface

2010

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In this paper, we present a theoretical study of the elastic deformations arising in the vicinity of the Si/ SiO 2 interface upon oxidation of a silicon substrate. The oxidation is modelized using an algorithm which alternates the inclusion of oxygen atoms and Molecular Dynamics simulations at high temperature. We find that the SiO 2 film undergoes an overall compressive state while a more complex strain field is found in the first few Si layers under the interface where tensile and compressive microstructures coexist, the former being definitely larger than the latter. The analysis of the formation energies of the main defects responsible for Si diffusion reveals that, in spite of the complexity of the deformation field at the Si/ SiO 2 interface, their dependence with respect to the local deformation obeys the same laws as those derived from the application of a simple biaxial stress.and PHYSICAL REVIEW B 81, 045315 ͑2010͒

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Section: Introductionmentioning

confidence: 99%

Atomistic modeling of strain and diffusion at theSi/SiO2interface

2010

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“…Several approaches for achieving enhanced mobility in CMOS devices are reviewed. Methods for achieving defect-free strained Si structures have also been discussed elsewhere [1].…”

Section: Introductionmentioning

confidence: 99%

Optimization of ClusterCarbon™ process parameters for strained Si lattice

Sekar¹,

Krull²,

Horsky³

et al. 2008

Materials Science and Engineering: B

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“…By using this method, we are able to get as good as trench profile image by Polishing. The 45° notch oriented device on <100> surface orientation wafer results in 10-20% PMOS transistor current gain without degradation on NMOS transistor [1]. This orientation challenges FA analyst in sample preparation.…”

Section: Introductionmentioning

confidence: 99%