Improve clock tree efficiency for low power clock tree design

Ge, Zhe; Fu, Juan; Wang, Peidong; Wang, Lei

doi:10.1109/icsict.2016.7999057

Cited by 2 publications

(1 citation statement)

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“…Fig. 1 shows the synchronous driving principle of the small array CMOS image sensor, which ensures the timing consistency of the dual driving circuit through the clock tree layout technology in the design of digital integrated circuits [33,34,35]. If this idea is directly applied to the design of large array CMOS image sensor with stitching technology, as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

Guo

2020

IEICE Electron. Express

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A synchronous driving approach for stitching CMOS image sensor is proposed. Dual terminal signal line driver structure must be considered in the design of row control for high definition CMOS image sensor pixel array. However, as the size of the array increases further, the traditional synchronization technologies such as clock tree cannot be applied because of the stitching technology. Furthermore, this invalidity will cause DC shoot through and dead line. Based on the adaptive delay phase-locked loop, dual terminal signal line driver with highly efficient synchronization for pixel array is realized in a single die CMOS image sensor with 225M pixels and large area of 120 × 120 mm 2. The comparison results show that the timing matching improves by two orders of magnitude, and the consistency reaches 99.95%.

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Section: Introductionmentioning

confidence: 99%