A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

Abstract

A synchronous driving approach for stitching CMOS image sensor is proposed. Dual terminal signal line driver structure must be considered in the design of row control for high definition CMOS image sensor pixel array. However, as the size of the array increases further, the traditional synchronization technologies such as clock tree cannot be applied because of the stitching technology. Furthermore, this invalidity will cause DC shoot through and dead line. Based on the adaptive delay phase-locked loop, dual terminal signal line driver with highly efficient synchronization for pixel array is realized in a single die CMOS image sensor with 225M pixels and large area of 120 × 120 mm 2. The comparison results show that the timing matching improves by two orders of magnitude, and the consistency reaches 99.95%.

Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique

“…Through the above simulation results in the case of different wire widths, power supply internal resistances, temperatures, and corners, it can be concluded that the adaptive correction technology based on delay detection and accurate compensation has high reliability. As shown in the comparison of specifications in Table 1, the non-synchronization after the correction is less than 2 ns, which is slightly worse than the non-synchronization of less than 1 ns achieved via the PLL correction technique adopted in Reference [15]. However, the method proposed in this paper uses a digital circuit with very low power consumption.…”

“…In Reference [ 14 ], the timing skew is detected in the digital domain through a correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In Reference [ 15 ], the reason why clock tree technology cannot solve this problem is explained in detail, and a delay-locked loop (DLL) design is proposed to improve the synchrony of both row driver signals. However, one DLL can only be used for one row logic signal; when there are multiple row logic signals to be synchronized, multiple delay-locked loops are required to work at the same time.…”

High-Linearity and High-Speed ROIC of Ultra-Large Array Infrared Detectors Based on Adaptive Compensation and Enhancement

“…Table 2 shows the comparison between the frame rate of the readout circuit designed in this paper and references [ 7 , 15 , 16 , 17 ]. It can be seen that the design method proposed in this paper can effectively improve the frame rate of the ultra-large array infrared readout circuit.…”

“…∆V FD is the voltage difference between two CDS voltages output by the FD point pixel, and ∆V OUT is the voltage difference between two CDS voltages output by a linearized circuit. The calculation results are shown in Equations ( 15) and (16).…”