Implementing sequential machines as self-timed circuits

David, I.; Ginosar, Ran; Yoeli, Michael

doi:10.1109/12.123378

IEEE Trans. Comput.

1992

DOI: 10.1109/12.123378

|View full text |Cite

Implementing sequential machines as self-timed circuits

I. David

Ran Ginosar

Michael Yoeli

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

1995

2006

Publication Types

Select...

Article6

Relationship

Self Cite0

Independent6

Authors

Journals

Cited by 17 publications

(1 citation statement)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…More than thirty years of research into asynchronous circuitry has produced a great variety of approaches [4,5], and phased logic has adopted concepts from several of these. For example, it uses one of an assortment of dual-rail signal encoding schemes [6][7][8] that combine both value and timing information. Dual-rail encoding originated in speed-independent design [9], and it serves as the foundation of phased logic's delay-insensitivity.…”

mentioning

confidence: 99%

Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry

Linder

Harden

1996

IEEE Trans. Comput.

View full text Add to dashboard Cite

Phased logic is proposed as a solution to the increasing problem of timing complexity in digital design. It is a delay-insensitive design methodology that seeks to restore the separation between logical and physical design by eliminating the need to distribute low-skew clock signals and carefully balance propagation delays. However, unlike other methodologies that avoid clocks, phased logic supports the cyclic, deterministic behavior of the synchronous design paradigm. This permits the designer to rely chiefly on current experience and CAD tools to create phased logic systems. Marked graph theory is used as a framework for governing the interaction of phased logic gates that operate directly on Level-Encoded two-phase Dual-Rail (LEDR) signals. A synthesis algorithm is developed for converting clocked systems to phased logic systems and is applied to benchmark examples. Performance results indicate that phased logic tends to be tolerant of logic delay imbalances and has predictable worst-case timing behavior. Although phased logic requires additional circuitry, it has the potential to shorten the design cycle by reducing timing complexities.

show abstract

mentioning

confidence: 99%

Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry

Linder

Harden

1996

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

Self-timed is self-checking

1995

View full text Add to dashboard Cite

Libraries in National Literacy Education Programmes in Africa South of the Sahara: The state-of-the-art

Newa

1990

International Library Review

View full text Add to dashboard Cite

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

Implementing sequential machines as self-timed circuits

Cited by 17 publications

References 2 publications

Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry

Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry

Self-timed is self-checking

Libraries in National Literacy Education Programmes in Africa South of the Sahara: The state-of-the-art

Contact Info

Product

Resources

About