Implementing latency-insensitive dataflow blocks

ACM Trans. Embed. Comput. Syst.

Townsend

Barker

et al. 2019

Self Cite

We present a technique for implementing dataflow networks as compositional hardware circuits. We first define an abstract dataflow model with unbounded buffers that supports data-dependent blocks (mux, demux, and nondeterministic merge); we then show how to faithfully implement such networks with bounded buffers and handshaking. Handshaking admits compositionality: our circuits can be connected with or without buffers, and combinational cycles arise only from a completely unbuffered cycle. While bounding buffer sizes can cause the system to deadlock prematurely, the system is guaranteed to produce the same, correct, data before then. Thus, unless the system deadlocks, inserting or removing buffers only affects its performance. We demonstrate how this enables design space to be explored.

“…2. A point-to-point link and its protocol [6]: valid indicates the data lines carry a token; ready indicates downstream is willing to consume a token.…”

Section: Hardware Dataflow Actorsmentioning

confidence: 99%

“…8. A data (pipeline) buffer, after Cao et al [6]. This breaks combinational paths in the data/valid network.…”

Section: Data and Control Buffersmentioning

confidence: 99%

Compositional Dataflow Circuits

ACM Trans. Embed. Comput. Syst.

Townsend

Barker

et al. 2019

Self Cite

“…The processing element design is based on our recent MEMOCODE publication [1]. That design provides provably correct asynchronous communication on multiple input/output channels, which can be tricky in cases where one output channel is consumed by the downstream operator while another output channel is blocked.…”

Section: Element Designmentioning

confidence: 99%

“…As shown in Figure 2, a channel consists of data, a valid bit that indicates data is present and must not be dropped, and a stop signal indicating backpressure. A pair of buffers speak this protocol on both their inputs and outputs and input sequences are provably preserved [1]. Figure 2 shows a two-input, two-output processing element.…”

Section: Element Designmentioning

confidence: 99%

Deadlock-free joins in DB-mesh, an asynchronous systolic array accelerator

Cao

Ross

Proceedings of the 13th International Workshop on Data Management on New Hardware

et al. 2017

Self Cite

Previous database accelerator proposals such as the Q100 provide a fixed set of database operators, chosen to support a target query workload. Some queries may not be well-supported by a fixed accelerator, typically because they need more resources/operators of a particular kind than the accelerator provides. By Amdahl's law, these queries become relatively more expensive as they are not fully accelerated. We propose a second-level accelerator, DB-Mesh, to take up some of this workload. DB-Mesh is an asynchronous systolic array that is more generic than the Q100, and can be configured to run a variety of operators with configurable parameters such as record widths. We demonstrate DB-Mesh applied to nested loops joins, an operator that is not directly supported on the Q100. We show that a naïve implementation has the potential for deadlock, and show how to avoid deadlock with a careful design. We also demonstrate how the data flow policy used in the array influences system throughput.

“…We present a compiler that synthesizes dataflow networks from algorithms expressed in a functional intermediate representation (IR) dubbed "Floh." We target dataflow networks because they are modular, inherently parallel, naturally "patient" about long, varying latencies, and they can yield high-speed hardware implementations [7]. We start from what is effectively a pure functional language to provide inherent parallelism and high-level abstractions to the designer, making it simple to correctly express and reason about complex parallel algorithms [17].…”

Section: Introductionmentioning

confidence: 99%

From functional programs to pipelined dataflow circuits

Townsend

Kim

Proceedings of the 26th International Conference on Compiler Construction

2017

Self Cite

We present a translation from programs expressed in a functional IR into dataflow networks as an intermediate step within a Haskellto-Hardware compiler. Our networks exploit pipeline parallelism, particularly across multiple tail-recursive calls, via non-strict function evaluation. To handle the long-latency memory operations common to our target applications, we employ a latency-insensitive methodology that ensures arbitrary delays do not change the functionality of the circuit. We present empirical results comparing our networks against their strict counterparts, showing that nonstrictness can mitigate small increases in memory latency and improve overall performance by up to 2×.