Compositional Dataflow Circuits

Edwards, Stephen A.; Townsend, Richard; Barker, Martha; Kim, Martha A.

doi:10.1145/3274280

Cited by 9 publications

(2 citation statements)

References 36 publications

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“…Different authors exploited latency-insensitive protocols [8], [15], [21] to construct synchronous and asynchronous dataflow circuits. Elastic circuits [15] are probably the best-studied form of latency-insensitivity, but the original paradigm is too restrictive for HLS.…”

Section: Related Workmentioning

confidence: 99%

From C/C++ Code to High-Performance Dataflow Circuits

Josipović

Guerrieri

Ienne

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where performance is limited by long latency control decisions. In this work, we describe an HLS approach which generates dynamically scheduled, dataflow circuits out of imperative code. We detail a complete set of rules to transform a standard compiler intermediate representation into a high-performance dataflow circuit that is able to dynamically resolve memory dependences and adapt its behavior on the fly to particular control flow decisions and operation latencies. Compared to a traditional HLS tool, the result is a different trade-off between performance and circuit complexity: statically scheduled circuits display the best performance per cost in regular applications, but general-purpose, irregular, and control-dominated computing tasks require the runtime flexibility of dynamic scheduling. Therefore, enabling dynamic behavior in HLS is key to dealing with the increasing computational demands of new contexts and broader application domains.

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Section: Related Workmentioning

confidence: 99%

From C/C++ Code to High-Performance Dataflow Circuits

Josipović

Guerrieri

Ienne

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Latency-insensitive protocols [3,6,9] have been explored as a way to overcome the limitations of static scheduling and offer the flexibility needed for true speculation [11]. Several latency-insensitive approaches [4,5,10] describe early evaluationpredicated execution based on special tokens which discard mispredicted data.…”

Section: Related Workmentioning

confidence: 99%

Speculative Dataflow Circuits

Josipović

Guerrieri

Ienne

2019

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract parallelism in irregular and control-dominated applications, dynamic scheduling opens a door to speculative execution, one of the most powerful ideas in computer architecture. Speculation allows executing certain operations before it is known whether they are correct or required: it can significantly increase fine-grain parallelism in loops where the condition takes many cycles to compute; it can also increase the performance of circuits limited by potential dependencies by assuming independence early on and by reverting to the correct execution if the prediction was wrong. In this work, we detail our methodology to enable tentative and reversible execution in dynamically scheduled dataflow circuits. We create a generic framework for handling speculation in dataflow circuits and show that our approach can achieve significant performance improvements over traditional circuit generation techniques.

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Accelerator Design with High-Level Synthesis

Pilato

Soldavini

2022

Handbook of Computer Architecture

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Specialized accelerators can exploit spatial parallelism on both operations and data thanks to a dedicated microarchitecture with a better use of the hardware resources. Designers need to describe such components (including the resources, their interconnections, and the control logic) in proper hardware languages compatible with synthesis tools. This process requires hardware design skills that are uncommon in software programmers. To boost the use of spatial accelerators, software programmers need automated methods, like high-level synthesis (HLS), to specify hardware blocks with high-level languages and automatically translate their specifications into the corresponding hardware descriptions ready for synthesis. While HLS is a key enabling technology for the design of complex hardware/software architectures, developing efficient spatial accelerators requires efficient HLS methods to co-optimize performance and hardware cost with a hardware/software co-design approach. In this chapter, we present the current state of the art in high-level synthesis, covering all steps to create the specialized microarchitecture of an accelerator. We also discuss outstanding challenges that can be addressed with the use of HLS.

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Compositional Dataflow Circuits

Cited by 9 publications

References 36 publications

From C/C++ Code to High-Performance Dataflow Circuits

From C/C++ Code to High-Performance Dataflow Circuits

Speculative Dataflow Circuits

Accelerator Design with High-Level Synthesis

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