From functional programs to pipelined dataflow circuits

Townsend, Richard; Kim, Martha A.; Edwards, Stephen A.

doi:10.1145/3033019.3033027

Cited by 27 publications

(16 citation statements)

References 29 publications

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“…A different approach is HLS from functional languages [12,15,27], and dataflow languages [11,13,25]. For example Townsend et al [27] uses a subset of Haskell and perform a syntax-directed translation to a internal dataflow representation which ultimately translated into a hardware design. Those works are closer to ours, as applications are expressed using high-level platform-agnostic patterns.…”

Section: Related Workmentioning

confidence: 99%

High-level synthesis of functional patterns with Lift

Kristien

Bodin

Steuwer

et al. 2019

Proceedings of the 6th ACM SIGPLAN International Workshop on Libraries, Languages and Compilers for Array Programming

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High-level languages are commonly seen as a good fit to tackle the problem of performance portability across parallel architectures. The Lift framework is a recent approach which combines high-level, array-based programming abstractions, with a system of rewrite-rules that express algorithmic as well as low-level hardware optimizations. Lift has successfully demonstrated its ability to address the challenge of performance portability across multiple types of CPU and GPU devices by automatically generating code that is on-par with highly optimized hand-written code.This paper demonstrates the potential of Lift for targeting FPGA-based platforms. It presents the design of new Lift parallel patterns operating on data streams, and describes the implementation of a Lift VHDL backend. This approach is evaluated on a Xilinx XC7Z010 FPGA using matrix multiplication, leading to a 10x speed-up over highly optimized CPU code and a commercial HLS tool. Furthermore, by considering the potential of design space exploration enabled by Lift, this work is a stepping stone towards automatically generated competitive code for FPGAs.

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Section: Related Workmentioning

confidence: 99%

High-level synthesis of functional patterns with Lift

Kristien

Bodin

Steuwer

et al. 2019

Proceedings of the 6th ACM SIGPLAN International Workshop on Libraries, Languages and Compilers for Array Programming

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“…Practically, nondeterministic merge processes expose the timing of a dataflow system implementation by interleaving sequences according to when tokens arrive at their inputs, and thus are used to improve performance or break a deadlock by avoiding the need to wait. For example, in the dataflow networks we obtain from syntax-directed translation [43], we use nondeterministic merge processes to share resources as shown in Figure 6, which we will explain in more detail in Section 3.4.…”

Section: Nondeterministic Mergementioning

confidence: 99%

“…We present a limited, core group of actors that we have found is rich enough to implement a wide variety of algorithms (see Townsend et al [43]). Our framework could support additional actor types, but their design is outside the scope of this article.…”

Section: Hardware Dataflow Actorsmentioning

confidence: 99%

“…By design, a dataflow network generated from a syntax-directed translation of a structured program (e.g., Dennis [13]) never requires the accumulation of an unbounded number of tokens to run, so inserting buffers according to a simple policy suffices to prevent these networks from deadlocking. We use such a policy for the networks we generate from Haskell programs [43], the original motivation for our work, but such a technique often inserts more buffers and hence more latency than strictly necessary. Our complete translation of Haskell assumes a sufficiently large heap, since the Haskell programs we translate can require unbounded memory to run to completion.…”

Section: Introductionmentioning

confidence: 99%

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Compositional Dataflow Circuits

Edwards

Townsend

Barker

et al. 2019

ACM Trans. Embed. Comput. Syst.

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We present a technique for implementing dataflow networks as compositional hardware circuits. We first define an abstract dataflow model with unbounded buffers that supports data-dependent blocks (mux, demux, and nondeterministic merge); we then show how to faithfully implement such networks with bounded buffers and handshaking. Handshaking admits compositionality: our circuits can be connected with or without buffers, and combinational cycles arise only from a completely unbuffered cycle. While bounding buffer sizes can cause the system to deadlock prematurely, the system is guaranteed to produce the same, correct, data before then. Thus, unless the system deadlocks, inserting or removing buffers only affects its performance. We demonstrate how this enables design space to be explored.

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“…This is also the case of Floh language described in Ref. [5]. A Floh program is translated into a dataflow graph using a very small set of types of actor and buffer, presented in details in Ref.…”

Section: Introductionmentioning

confidence: 99%

Actors with stretchable access patterns

Domas

Lenczner

2019

Integration

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In this article, we propose a new framework based on dataflow graphs to abstract and analyze designs for hard-ware architectures. It is called Actors with Stretchable Access Patterns (ASAP). It can overcome some limitations of all Static Data Flow (SDF) based models like mandatory buffering between actors. This article details the fundamental contributions of ASAP. Firstly, it gives the definition of actors and their different patterns. It also illustrates the link between these notions and components written in VHDL through several examples. Secondly, it presents the main algorithms to check if a graph processes an input data stream correctly, which is called compatibility checking. Thirdly, it summarizes the principles of graph modification to enforce this correctness in case of some blocks are declared incompatible. Finally, it briefly describes our EDA tool called BlAsT which integrates the above principles, before presenting an application on a realistic FPGA design. It shows that ASAP overwhelms other models in terms of resources saving without any impact on the global latency. It also points out the ability of BlAsT to compute and to propose graph modifications and to generate the VHDL code of the whole design.

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From functional programs to pipelined dataflow circuits

Cited by 27 publications

References 29 publications

High-level synthesis of functional patterns with Lift

High-level synthesis of functional patterns with Lift

Compositional Dataflow Circuits

Actors with stretchable access patterns

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