High-level synthesis of functional patterns with Lift

Kristien, Martin; Bodin, Bruno; Steuwer, Michel; Dubach, Christophe

doi:10.1145/3315454.3329957

Cited by 18 publications

(22 citation statements)

References 28 publications

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“…We choose to not compare against additional, prior systems for compiling image processing applications to accelerators (Rigel [21], Darkroom [20], RIPL [44], and Lift [28]) because available implementations of these systems do not fit within our evaluation framework of automatically producing multiple throughput-area trade-offs.…”

Section: Discussionmentioning

confidence: 99%

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Type-directed scheduling of streaming accelerators

Durst

Feldman

Huff

et al. 2020

Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation

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Designing efficient, application-specialized hardware accelerators requires assessing trade-offs between a hardware module's performance and resource requirements. To facilitate hardware design space exploration, we describe Aetherling, a system for automatically compiling data-parallel programs into statically scheduled, streaming hardware circuits. Aetherling contributes a space-and time-aware intermediate language featuring data-parallel operators that represent parallel or sequential hardware modules, and sequence data types that encode a module's throughput by specifying when sequence elements are produced or consumed. As a result, well-typed operator composition in the space-time language corresponds to connecting hardware modules via statically scheduled, streaming interfaces.We provide rules for transforming programs written in a standard data-parallel language (that carries no information about hardware implementation) into equivalent spacetime language programs. We then provide a scheduling algorithm that searches over the space of transformations to quickly generate area-efficient hardware designs that achieve a programmer-specified throughput. Using benchmarks from the image processing domain, we demonstrate that Aetherling enables rapid exploration of hardware designs with different throughput and area characteristics, and yields results that require 1.8-7.9× fewer FPGA slices than those of prior hardware generation systems.

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Section: Discussionmentioning

confidence: 99%

“…Dahlia [34] uses affine types to produce predictable HLS designs by restricting memory access patterns. Both Cλash [5,45] and Lift [28,43] present data-parallel operators like those in Section 4 whose types can encode throughput. Aetherling extends these types to also encode the ordering of valids and invalids.…”

Section: Related Workmentioning

confidence: 99%

Type-directed scheduling of streaming accelerators

Durst

Feldman

Huff

et al. 2020

Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation

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“…Functional languages have properties that are believed to provide a more natural mapping to logic circuits [12]. Besides CλASH, functional descriptions are used for the input for the SPIRAL [51] and Lift [52] frameworks. They apply rewrite rules to lower the high-level sources towards various compute fabrics, including FPGA.…”

Section: Functional or Declarative Languagesmentioning

confidence: 99%

FPGA Acceleration for Big Data Analytics: Challenges and Opportunities

Hoozemans

Peltenburg

Nonnemacher³

et al. 2021

IEEE Circuits Syst. Mag.

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The big data revolution has ushered an era with ever increasing volumes and complexity of data requiring ever faster computational analysis. During this very same era, CPU performance growth has been stagnating, pushing the industry to either scale their computation horizontally using multiple nodes in datacenters, or to scale vertically using heterogeneous components to reduce compute time. However, networking and storage continue to provide both higher throughput and lower latency, which allows for leveraging heterogeneous components, deployed in data centers around the world. Still, the integration of big data analytics frameworks with heterogeneous hardware components such as GPGPUs and FPGAs is challenging, because there is an increasing gap in the level of abstraction between analytics solutions developed with big data analytics frameworks, and accelerated kernels developed with heterogeneous components. In this article, we focus on FPGA accelerators that have seen wide-scale deployment in large cloud infrastructures. FPGAs allow the implementation of highly optimized hardware architectures, tailored exactly to an application, and unburdened by the overhead associated with traditional general-purpose computer architectures. FPGAs implementing dataflow-oriented architectures with high levels of (pipeline) parallelism can provide high application throughput, often providing high energy efficiency. Latency-sensitive applications can leverage FPGA accelerators by directly connecting to the physical layer of a network, and perform data transformations without going through the software stacks of the host system. While these advantages of FPGA accelerators hold promise, difficulties associated with programming and integration limit their use. This article explores the existing practices in big data analytics frameworks, discusses the aforementioned gap in development abstractions, and provides some perspectives on how to address these challenges in the future.

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“…HLS has existed for many years, and it is very active in academic circles due to its short development and verification time. Many HLS-related DSLs have been proposed: Lift [7], Chisel, Bluespec [8], SpinalHDL, Lava [9], and Cλash [10] to implement functional programming, which improves the abstraction of hardware code, and has the following advantages: Automatic bit width inference deduction (even across module boundaries), error checking capability, Parameterization capability, a large number of basic components and reusable Intellectual Property core (IP). Although these methods take advantage of the characteristics of modern programming languages, they are essentially HDL, and the design of these languages is the only real correspondence with real circuits.…”

Section: Relate Workmentioning

confidence: 99%

A Highly Configurable High-Level Synthesis Functional Pattern Library

Huang

Gao

et al. 2021

Electronics

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FPGA has recently played an increasingly important role in heterogeneous computing, but Register Transfer Level design flows are not only inefficient in design, but also require designers to be familiar with the circuit architecture. High-level synthesis (HLS) allows developers to design FPGA circuits more efficiently with a more familiar programming language, a higher level of abstraction, and automatic adaptation of timing constraints. When using HLS tools, such as Xilinx Vivado HLS, specific design patterns and techniques are required in order to create high-performance circuits. Moreover, designing efficient concurrency and data flow structures requires a deep understanding of the hardware, imposing more learning costs on programmers. In this paper, we propose a set of functional patterns libraries based on the MapReduce model, implemented by C++ templates, which can quickly implement high-performance parallel pipelined computing models on FPGA with specified simple parameters. The usage of this pattern library allows flexible adaptation of parallel and flow structures in algorithms, which greatly improves the coding efficiency. The contributions of this paper are as follows. (1) Four standard functional operators suitable for hardware parallel computing are defined. (2) Functional concurrent programming patterns are described based on C++ templates and Xilinx HLS. (3) The efficiency of this programming paradigm is verified with two algorithms with different complexity.

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High-level synthesis of functional patterns with Lift

Cited by 18 publications

References 28 publications

Type-directed scheduling of streaming accelerators

Type-directed scheduling of streaming accelerators

FPGA Acceleration for Big Data Analytics: Challenges and Opportunities

A Highly Configurable High-Level Synthesis Functional Pattern Library

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