Type-directed scheduling of streaming accelerators

Abstract

Designing efficient, application-specialized hardware accelerators requires assessing trade-offs between a hardware module's performance and resource requirements. To facilitate hardware design space exploration, we describe Aetherling, a system for automatically compiling data-parallel programs into statically scheduled, streaming hardware circuits. Aetherling contributes a space-and time-aware intermediate language featuring data-parallel operators that represent parallel or sequential hardware modules, and sequence data types that encode a module's throughput by specifying when sequence elements are produced or consumed. As a result, well-typed operator composition in the space-time language corresponds to connecting hardware modules via statically scheduled, streaming interfaces.We provide rules for transforming programs written in a standard data-parallel language (that carries no information about hardware implementation) into equivalent spacetime language programs. We then provide a scheduling algorithm that searches over the space of transformations to quickly generate area-efficient hardware designs that achieve a programmer-specified throughput. Using benchmarks from the image processing domain, we demonstrate that Aetherling enables rapid exploration of hardware designs with different throughput and area characteristics, and yields results that require 1.8-7.9× fewer FPGA slices than those of prior hardware generation systems.

Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators

“…Lift-hls [19], Cλash [1] and Aetherling [10] have recently shown the advantages of functional IR. Similar to Shir's vector and stream types, these two feature space-and time-aware types to express parallelism and pipelining on a high level of abstraction.…”

“…Aetherling [10] has presented results on a larger set of applications. However, they have only demonstrated results in simulation using a simple memory model and have not discussed how memory would be handled on a real hardware.…”

“…Delite [36], Lift [34] and Futhark [12] have demonstrated that high-level abstractions and highperformance can go hand in hand. More recently, Lift-hls [19] and Aetherling [10] have demonstrated that the functional approach is viable for producing accelerators.…”

Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration

“…We classify related research literature across five dimensions, as shown in Table 3. The types of parallelism supported by each piece of research vary from ILP within Basic Block boundaries [33,34], to loop level [7,10,12,18], task level parallelism [16,19] and Tensor level [15]. Early DSE, one of the most important aspects of Trireme, is in many instances not supported by tools developed to expose and exploit parallelism in HW acceleration [12,15,16,20,24].…”

“…On the other hand, Spatial [10] is an early DSE infrastructure that uses Hypermapper 2.0 [18] in order to apply early DSE, however the parts to be accelerated need to be user-defined and high level languages are not supported as input. Aetherling [7] applies early DSE as well and can be configured onto FPGAs, but it is restricted to loop level parallelism only and, like Spatial, does not support high level languages (C/C++).…”