Implementing branch-predictor decay using quasi-static memory cells

Abstract

With semiconductor technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large on-chip array structures such as caches and branch predictors. Recent work has suggested that even larger branch predictors can and should be used in order to improve microprocessor performance. A further consideration is that more aggressive branch predictors, especially multiported predictors for multiple branch prediction, may be thermal hot spots, thus further increasing its leakage. Moreover, as the branch predictor holds state that is transient and predictive, elements can be discarded without adverse effect. For these reasons, it is natural to consider applying decay techniques-already shown to reduce leakage energy for caches-to branch-prediction structures.Due to the structural difference between caches and branch predictors, applying decay techniques to branch predictors is not straightforward. This paper explores the strategies for exploiting spatial and temporal locality to make decay effective for bimodal, gshare, and hybrid predictors, as well as the branch target buffer. Furthermore, the predictive behavior of branch predictors steers them towards decay based not on state-preserving, static storage cells, but rather quasi-static, dynamic storage cells. This paper will examine the results of implementing decaying branch predictor structures with dynamic-appropriately, decaying-cells rather than the standard static SRAM cell.Overall, this paper demonstrates that decay techniques can apply to more than just caches, with the branch predictor and BTB as an example. We show decay can either be implemented at the architectural level, or with a wholesale replacement of static storage cells with quasi-static storage cells which naturally implement decay. More importantly, decay techniques can be applied and should be applied to other such transient and/or predictive structures.

Leakage Energy Reduction in Value Predictors through Static Decay

“…quasi-static 4T transistors in the VP array, although similar leakage savings would be expected [9].…”

“…Kaxiras et al [10] successfully applied decay techniques to individual cache lines in order to reduce leakage in cache structures (67% of static power consumption can be saved with minimal performance loss). This technique has also been applied to conditional branch predictors and BTB structures [6] [9].…”

“…Rather, the 4T cell is charged upon each access, whether read or write, and it slowly leaks the charge over time until, eventually, the value stored is lost. In [9], it was proposed to apply decay techniques to branch predictors by using 4T cells. By doing this, some of the drawbacks of using gated-V DD transistors are eliminated, since an access to a 4T cell automatically reactivates the cell, whereas reactivating a 6T cell from the "sleep" mode is somewhat more complex, requiring extra hardware involved in gating the supply voltage.…”

“…Cache Decay [10] selectively turns individual data cache lines off if they have not been used in a long time, reducing leakage power at the cost of loosing the content of the cache line. This non-state preserving technique has also been successfully applied to branch predictors [6] [9].…”

Process Variation Tolerant 3T1D-Based Cache Architectures

“…The decay cache provides a fine-grained leakage control scheme by enabling Vdd-gating on a per-line basis after specified time intervals [13]. Juang et al recognized that quasi-static 4T cells could be used to avoid the need to implement Vdd-gating transistors and demonstrate power savings benefits in a decaying branch predictor [12]. None of the above works consider the impact of process variations and, hence, they do not consider the variety of line-level retention time mechanisms that we consider.…”