Leakage Energy Reduction in Value Predictors through Static Decay

Cebrian, Juan M.; Aragón, Juan L.; García, José M.

doi:10.1109/ipdps.2007.370537

Cited by 2 publications

(5 citation statements)

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“…We must reduce leakage in any possible structure, despite its size, as smaller and hotter structures can leak more than larger but cooler ones. In this paper we evaluate both state and nonstate preserving techniques for reducing leakage power in value predictors including Static Value Prediction Decay (SVPD) [4], Adaptive Value Prediction Decay (AVPD) [5] and a novel power-performance drowsy approach for Value Predictors. SVPD and AVPD are mechanisms able to dramatically reduce the leakage energy of traditional value predictors with negligible impact on neither prediction accuracy nor processor performance, even in the proposed pessimistic scenario where all instructions are predicted.…”

Section: Discussionmentioning

confidence: 99%

“…In previous papers we proposed the use of non-state preserving techniques for reducing leakage power in value predictors, including Static Value Prediction Decay (SVPD) [4] and Adaptive Value Prediction Decay (AVPD) [5]. These techniques either statically or dynamically locate VP entries that have not been accessed for a noticeable amount of time and switch them off to prevent leakage.…”

Section: Introductionmentioning

confidence: 99%

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Leakage-efficient design of value predictors through state and non-state preserving techniques

2010

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In the last decade computer engineers have faced changes in the way microprocessors are designed. New microprocessors do not only need to be faster than the previous generation, but also be feasible in terms of energy consumption and thermal dissipation. Recently, a new challenge appeared for computer engineers, the static power consumption. As process technology advances toward deep submicron, the static power component becomes a serious problem, especially for large on-chip array structures such as caches or prediction tables, and it must be taken into consideration. We can fight to reduce leakage power in two different ways: we can switch off the structure, reducing its leakage to zero but losing its contents (non-state preserving techniques), or we can lower its voltage (state preserving techniques), obtaining less savings but being able to restore the state of the structure in a reasonable time.Data dependences are one of the key factors that limit performance in modern microprocessors. Value Prediction (VP) is a paradigm that exploits value locality in order to predict the output of an instruction, overcoming data dependences. The more accurate the predictor, the more performance is obtained, at the expense of becoming a potential source of power consumption and a thermal hot spot.In this work we propose a leakage-efficient design of traditional Value Predictors (Stride, FCM, and DFCM) based on the fact that many VP entries remain unused during long periods of time before being eventually evicted. By applying both state and J.M. Cebrián ( ) · Leakage-efficient design of value predictors through state 29 non-state preserving techniques, the unused entries are disabled obtaining substantial leakage energy reductions (50-80% depending on the configuration and predictor type).

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Leakage-efficient design of value predictors through state and non-state preserving techniques

2010

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“…The static decay scheme suited for value predictors needs to detect those VP entries that have been unused for a significant period of time in order to switch them off [3]. But in order to successfully apply decay techniques, it is necessary to carefully choose the number of cycles we should wait before shutting an entry off in order to match generational changes.…”

Section: Static Decay Scheme For Value Predictorsmentioning

confidence: 99%

“…In order to precisely evaluate the net leakage energy savings provided by the static VP decay approach, it is necessary to consider the following overheads associated with the mechanism. The first component overhead takes into account the extra dynamic and static power that results from the additional hardware (a global decay interval counter as well as the two-bit local counters 2 per VP entry [3]). The second component overhead is derived from the induced VP misses (when a VP entry is prematurely disabled) that increase execution time.…”

Section: Static Decay Scheme For Value Predictorsmentioning

confidence: 99%

“…The AVPD mechanism works as follows (see Figure 7): each cycle the global decay counter is incremented by one and, when it 3 Using a hierarchical counter is more power-efficient since it allows accessing the local counters at a much coarser level. Accessing the local counters each cycle would be prohibitive because of the associated power overhead.…”

Section: Adaptive Value Prediction Decay (Avpd)mentioning

confidence: 99%

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Adaptive VP decay

Cebrian

Aragón

García

2007

Proceedings of the 4th International Conference on Computing Frontiers

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Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward deep submicron, static power dissipation becomes a new challenge to address, especially for large on-chip array structures such as caches or prediction tables. Value prediction emerged in the recent past as a very effective way of increasing processor performance by overcoming data dependences. The more accurate the value predictor is the more performance is obtained, at the expense of becoming a source of power consumption and a thermal hot spot, and therefore increasing its leakage. Recent techniques, aimed at reducing the leakage power of array structures such as caches, either switch off (non-state preserving) or reduce the voltage level (statepreserving) of unused array portions.In this paper we propose the design of leakage-efficient value predictors by applying adaptive decay techniques in order to disable unused entries in the prediction tables. As value predictors are implemented as non-tagged structures an adaptive decay scheme has no way to precisely determine the induced miss-ratio due to prematurely decaying an entry. This paper explores adaptive decay strategies suited for the particularities of value predictors (Stride, DFCM and FCM) studying the tradeoffs for these prediction structures, that exhibit different pattern access behaviour than caches, in order to reduce their leakage energy efficiently compromising neither VP accuracy nor the speedup provided. Results show average leakage energy reductions of 52%, 70% and 80% for the Stride, DFCM and FCM value predictors of 20 KB respectively.

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Leakage Energy Reduction in Value Predictors through Static Decay

Abstract: As process technology advances toward deep submicron (below 90nm)

Cited by 2 publications

References 19 publications

Leakage-efficient design of value predictors through state and non-state preserving techniques

Leakage-efficient design of value predictors through state and non-state preserving techniques

Adaptive VP decay

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