Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections

Lin, Chang-Yi; Yang, Haw‐Ching; Wang, Wei Chung; Fang, Weileun

doi:10.1088/0960-1317/17/6/014

Cited by 46 publications

(26 citation statements)

References 16 publications

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“…Moreover, the step coverage of metal-based alloys is not as good as the glass-frit, since the thickness of these alloys is typically limited to few micrometers, mostly due to their high stress. There are also examples of verticallytransferred sensor leads in the literature [12]- [18]. These approaches typically require the drilling of the silicon or glass substrates by using a laser [12], DRIE [13]- [15], or wet etching [16], [17] and then hermetic filling of these trenches with thermal oxidation [15], metal bumps/patterning [16], [17], glass reflow [13], [14], or metal electroplating [12], [18].…”

Section: Introductionmentioning

confidence: 99%

“…These approaches typically require the drilling of the silicon or glass substrates by using a laser [12], DRIE [13]- [15], or wet etching [16], [17] and then hermetic filling of these trenches with thermal oxidation [15], metal bumps/patterning [16], [17], glass reflow [13], [14], or metal electroplating [12], [18]. Therefore, they either suffer complex process steps such as void-free hermetic-filling of the feedthrough openings [12], [15] or trench-refill processes [13], [16], [18]. Another challenge with the vertical feedthrough processes is to ensure precise control of the thicknesses and the relative offsets of the sealing material, sensor leads, sealing regions, and vertical feedthroughs [18], in order to achieve the sealing and the lead transfer simultaneously.…”

Section: Introductionmentioning

confidence: 99%

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Advanced MEMS Process for Wafer Level Hermetic Encapsulation of MEMS Devices Using SOI Cap Wafers With Vertical Feedthroughs

Torunbalcı

Alper

Akın

2015

J. Microelectromech. Syst.

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This paper reports a novel and inherently simple fabrication process, so-called advanced MEMS (aMEMS) process, that is developed for high-yield and reliable manufacturing of wafer-level hermetic encapsulated MEMS devices. The process enables lead transfer using vertical feedthroughs formed on an Silicon-On-Insulator (SOI) wafer without requiring any complex via-refill or trench-refill processes. It requires only seven masks to fabricate the hermetically capped sensors with an experimentally verified process yield of above 80%. Hermetic encapsulation is achieved by Au-Si eutectic bonding at 400°C, and the pressure inside the encapsulated cavity has been characterized to be as low as 1 mTorr with successfully activated thin-film getters. The pressure inside the encapsulated cavity can also be adjusted in the range of 1 mTorr-5 Torr by various combinations of outgassing and gettering options in order to satisfy the requirements of different applications. The package pressure is being monitored for the selected chips and is observed to be stable below 10 mTorr since their fabrication about 10 months ago. The shear strengths of several packages are measured to be as high as 30 MPa with average shear strength of 22 MPa, indicating a mechanically strong bonding. The robustness of the packages is tested by thermal cycling between 100°C and 25°C, and absolutely no degradation is observed in the hermeticity and the package pressure. The package pressure is also verified to remain unchanged after storing the packages at a high storage temperature of 150°C for 24 h. Furthermore, the packaged chips are observed to withstand a high temperature shock test performed at 300°C for 5 min, at the end of which the characteristics of the encapsulated sensor indicates that the package still remains hermetic (no detectable leaks) and also the package pressure remains constant at ∼20 mTorr.[ 2014-0338]Index Terms-Microelectromechanical systems (MEMS), wafer level hermetic encapsulation, Au-Si eutectic bonding, vertical feedthroughs, advanced MEMS process (aMEMS).

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Advanced MEMS Process for Wafer Level Hermetic Encapsulation of MEMS Devices Using SOI Cap Wafers With Vertical Feedthroughs

Torunbalcı

Alper

Akın

2015

J. Microelectromech. Syst.

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“…For instance, approaches to fabricate through-wafer vias in a capping wafer have been reported [6,7]. Through-wafer vias embedded inside the substrate of MEMS devices are employed in [8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Implementation of silicon-on-glass MEMS devices with embedded through-wafer silicon vias using the glass reflow process for wafer-level packaging and 3D chip integration

Lin

Hsu

Yang

et al. 2008

J. Micromech. Microeng.

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This study presents a novel system architecture to implement silicon-on-glass (SOG) MEMS devices on Si-glass compound substrate with embedded silicon vias. Thus, the 3D integration of MEMS devices can be accomplished by means of through-wafer silicon vias. The silicon vias connecting to the pads of devices are embedded inside the Pyrex glass. Parasitic capacitance for both vias and microstructures is decreased and mismatch of coefficient of thermal expansion (CTE) is reduced. In applications, the glass reflow process together with the SOG micromachining processes were employed to implement the presented concept. Successful driving of the resonator through the silicon vias is demonstrated. The wafer-level hermetic packaging can be further achieved by anodic bonding of a Pyrex7740 wafer. Hermeticity of the packaged device performed by helium leak test satisfied MIL-STD-883E. The packaged SOG device is SMT (surface mount technology) compatible and ready for 3D microsystem integration.

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“…In the last decades through wafer electrical connections became a more and more important issue for different applications, mainly for 3D integration of MEMS (Micro-Electro-Mechanical systems), like wafer-level packaging or vertical connections in multi-wafer devices [1][2]. Manufacturing involve two problems: through wafer via holes manufacturing and holes filling with a conductive layer.…”

Section: Introductionmentioning

confidence: 99%

Variable isotropy Deep RIE process for through wafer via holes manufacturing

Vasilache

Colpo²,

Giacomozzi³

et al. 2011

SPIE Proceedings

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This paper reports a method on the manufacturing of through wafer via holes in silicon with tapered walls by Deep Reactive Ion Etching (DRIE) using the opportunity to change the isotropy in the DRIE equipments during processing. By using consecutively anisotropic and isotropic etching steps it is possible to enlarge the dimension of via holes on one side of the wafer, while on the other side dimension is set by the initial etching window.The method was used for two etching windows sizes (100μm and 20μm respectively) on 200μm and 300μm thick wafers. The aim was to manufacture tapered walls via having a good control over the walls angle. Different Bosch process recipes providing different walls roughness were used. Via holes with tapered walls (2° to 22°) were manufactured using this method. An angle deviation smaller than 10% of the manufactured via holes along the wafers was observed.

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Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections

Cited by 46 publications

References 16 publications

Advanced MEMS Process for Wafer Level Hermetic Encapsulation of MEMS Devices Using SOI Cap Wafers With Vertical Feedthroughs

Advanced MEMS Process for Wafer Level Hermetic Encapsulation of MEMS Devices Using SOI Cap Wafers With Vertical Feedthroughs

Implementation of silicon-on-glass MEMS devices with embedded through-wafer silicon vias using the glass reflow process for wafer-level packaging and 3D chip integration

Variable isotropy Deep RIE process for through wafer via holes manufacturing

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