Implementation of the Chien search algorithm on application specific instruction set processor

Lee, Hyunseok; Lee, Youngseok; Yang, Ho

doi:10.1109/icce.2012.6161820

Cited by 2 publications

(1 citation statement)

References 3 publications

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“…The designed divider is also able to handle the special case in which the most significant symbol of the syndrome is zero. Errors positions and values evaluation has been carried out with well-established Chien [25] and Forney [15,26] methods respectively. The whole designed architecture is, also in this case, pipe-lined.…”

Section: Reed-solomonmentioning

confidence: 99%

Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction

et al. 2020

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In modular distributed architectures, the adoption of a communication method that is at the same time robust and has a low and predictable latency is of utmost importance in order to support the required system dynamics. The aim of this paper is to evaluate the consequences of the random jitter on machine drives distributed control, caused by the messages’ re-transmission in case of an error in the received data. To achieve this goal, two different Forward Error Correction (FEC) techniques are introduced in the chosen protocol, so that the recipient of the message can correct random errors without the need of any additional round trip delays needed to request and obtain a re-transmission. Experimentally validated simulations are used to evaluate the impact of random network derived jitter on a real world closed loop control system for distributed power electronic converters.

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Section: Reed-solomonmentioning

confidence: 99%