Minimization of Network Induced Jitter Impact on FPGA-Based Control Systems for Power Electronics through Forward Error Correction

Abstract

In modular distributed architectures, the adoption of a communication method that is at the same time robust and has a low and predictable latency is of utmost importance in order to support the required system dynamics. The aim of this paper is to evaluate the consequences of the random jitter on machine drives distributed control, caused by the messages’ re-transmission in case of an error in the received data. To achieve this goal, two different Forward Error Correction (FEC) techniques are introduced in the chosen protocol, so that the recipient of the message can correct random errors without the need of any additional round trip delays needed to request and obtain a re-transmission. Experimentally validated simulations are used to evaluate the impact of random network derived jitter on a real world closed loop control system for distributed power electronic converters.

A Scalable System Architecture for High-Performance Fault Tolerant Machine Drives

“…The traditional approach of error detection and message retransmission can deal with numerous random errors while having minimal impact on the transmission efficiency during nominal operation. The downside of this process is the introduction of a large amount of jitter when a packet needs to be retransmitted, potentially leading to control instability or deadline violations [17]. An alternative strategy, adopted in the designed protocol, is the use of Forward Error Correction (FEC), where enough redundancy is added to the bit stream to enable the receiver to mathematically reconstruct the original bit pattern, completely avoiding the need for retransmission.…”

Multiphase fault tolerant distributed control techniques for integrated drives based on resonant regulators

“…The power electronics hardware consists of six separate single phase cells, each one controlling a single phase. These are all connected to a centralised control structure through a custom, point to point, low latency, power electronics digital communication protocol [6]. While this design decision, on the surface, introduces a single point of failure, in the controller.…”

“…One possible way to address this issue is to distribute the power electronics, separating the usually completely integrated drives, in several independent cells, each one of them responsible to control a single phase. This eliminates the parasitic elements through physical and electrical separation, decreasing the chance of a secondary fault [6].…”

Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices

“…These power controls generally lack precision and do not work in real time; to overcome these limitations, different solutions relying on FPGA (Field Programmable Gate Array)-implemented algorithms can be exploited [5]. In the last few years, the application of FPGA devices has increased exponentially in a wide variety of fields, such as: digital signal processing [6][7][8][9][10], data processing [11,12], bioinformatics [13,14] and power electronics [15][16][17]. Among the applications based on FPGAs that recently have been applied to the smart grid field, MPC (Model Predictive Control) has particular importance [18][19][20].…”