Implementation of safety critical logic controller by means of FPGA

Węgrzyn, Marek

doi:10.1016/s1367-5788(03)00007-5

Cited by 17 publications

(13 citation statements)

References 5 publications

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“…Boolean expressions called guards describe the external conditions for transitions to be enabled. In the example in figure 2 [20] 10 . The second order macroplace mp 11 is built from two parallel macroplaces mp 4 and mp 5 .…”

Section: Sample Application For Logic Controllermentioning

confidence: 99%

“…The configuration place mp 8 , which can be redundant during next steps of logic design, points to the third order subnet. The configuration places {mp 3 , mp 6 , mp 7 , mp 9 , mp 10 , mp 11 } are sufficient to represent the activity of all Petri net places, which are dominated by them.…”

Section: Sample Application For Logic Controllermentioning

confidence: 99%

“…For description of local state changes inside macroplace mp 10 after encoding only two equations are required:…”

Section: Monolithic Modular Logic Synthesismentioning

confidence: 99%

“…LDs [5,6], SFCs [7], FSMs [8], statecharts, Petri nets [1,9], or HDLs [6,8,10]. However, for safety critical applications only very well verified methods can be applied [10,11,12].…”

Section: Introductionmentioning

confidence: 99%

“…The design process is supplemented by dual verification. It is based on the on simulation of both models and results comparison [10,19]. Additional methods of testing and analysis [20] can extend verification process at the earlier stage.…”

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confidence: 99%

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Dual synthesis of Petri net based application specific logic controllers with increased safety

Tkacz¹,

Bukowiec²,

Adamski³

2016

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. In the paper, design flow of the application specific logic controllers with increased safety by means of Petri nets is proposed. The controller architecture is based on duplicated control unit and comparison results from both units. One specification of control algorithm is used by means of Petri net for both units. The hardware duplication is obtained during dual synthesis process. This process uses two different logic synthesis methods to obtain two different hardware configurations for both control units. Additionally, the dual verification is applied to increase reliability of the control algorithm. Such design flow simplifies the process of realization of control systems with increased safety.

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Section: Sample Application For Logic Controllermentioning

confidence: 99%

Section: Sample Application For Logic Controllermentioning

confidence: 99%

“…For description of local state changes inside macroplace mp 10 after encoding only two equations are required:…”

Section: Monolithic Modular Logic Synthesismentioning

confidence: 99%

“…LDs [5,6], SFCs [7], FSMs [8], statecharts, Petri nets [1,9], or HDLs [6,8,10]. However, for safety critical applications only very well verified methods can be applied [10,11,12].…”

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Dual synthesis of Petri net based application specific logic controllers with increased safety

Tkacz¹,

Bukowiec²,

Adamski³

2016

Bulletin of the Polish Academy of Sciences Technical Sciences

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9 PeNLogic – System for Concurrent Logic Controllers Design

Węgrzyn

2011

Design of Digital Systems and Devices

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Abstract. In the paper the CAD system dedicated for modeling, verification, and synthesis of concurrent controllers modeled by interpreted Petri net is presented. Petri net model can be prepared as graph or as textual form. Controllers specified by Petri nets can be analyzed and implemented using method suitable for such model. For verification of Petri net another part of system is used. Moreover, the results of verification are decomposition of net into several communicating state machines (as finite state machines, FSMs). After verification it is possible to transform Petri net model into HDLs model (VHDL and Verilog) and alternatively into EDIF or XNF netlist format. Such prepared models are also simulated and synthesized using other academic or commercial CAD systems. The system has been developing at University of Zielona Góra. Development of new methods of modeling, verification and synthesis has been contributed to make an attempt the new integrated version of the system. In addition, using of Java environment gives opportunity to work out the system that is platform independent. IntroductionThe specific application often dictates the system design requirements, such as modularity and flexibility. In general, the design procedure involves the integration of analytical and graphical descriptions. Graphical descriptions, such as control-interpreted Petri nets [11], SFC (Sequential Function Chart) [8] and Grafcet [7], provide established techniques for proper system designs. They have helped industrial engineers to understand the system behavior and performance over many years.A behavioral representation describes the system's functionality independently of its implementation. It treats a system as a black box, and defines how the black box responds to any combination of input values. The process of designing a system proceeds from a behavioral specification (SFC diagram or Petri net) to a programmable logic implementation (FPGA, Field Programmable Gate Array). A design in purely behavioral form, like a Petri net, is converted into an intermediate rule-based description, void of any technology-specific implementation details. The final FPGA implementation is generated by automatic synthesis using CAD

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Dual Simulation of Application Specific Logic Controllers Based on Petri Nets

Bukowiec

Tkacz

2014

Lecture Notes in Electrical Engineering

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Abstract. The paper describes a new method of verification of the application specific logic controllers designed with use of Petri net. The method is oriented on behavioral simulation of post synthesis models. Two different method of logic synthesis are preformed for the same control algorithm described as Petri net. Then, obtained HDL models are used for dual simulation with result comparison. It allows to detect ambiguous construct in designed control algorithm.Keywords: logic controller, Petri net, simulation. IntroductionThe paper presents a new method of dual simulation of the application specific logic controllers (ASLCs). ASLCs [1][2][3][4][5] are one of the biggest group of electronic circuits.The most classical way of designing such controllers is application of hardware description languages (HDLs) but it is annoying for designer and possibly it gives high risk of human mistake. The usage of graphical representation of control algorithm is much more conformable [6][7][8]. Now, Petri nets (PNs) [9,10] are one of the most adequate methods for formal design of such controllers [11]. It gives a simple way for representation of concurrent processes and application of interpretation gives a possibility to exchange information with environment. Additionally, there could be applied mathematical algorithms for formal analysis and verification of the designed model [12][13][14][15]. Although these algorithms are able to detect defects, like liveness or reachability, in Petri net structure but they are not able to detect nondeterministic behavior of the algorithm. Typically the nondeterministic behavior of the algorithm is caused by a human mistake and it does not affect Petri net structure. To detect such mistake there have to be performed the simulation of the control algorithm and the comparison of its results with expected ones. It is very arduous process and it does not give expected results because it is also loaded with human mistake. The solution for this problem is dual simulation [16,17] with automated results comparison. Although currently only behavioral HDL description is used for such approaches and it is oriented on increase of simulation reliability. It allows also to detect some nondeterministic behavior but while the simulation is on behavioral level not connected to a hardware realization it does not ensure that all of them will be detected and controller

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Implementation of safety critical logic controller by means of FPGA

Cited by 17 publications

References 5 publications

Dual synthesis of Petri net based application specific logic controllers with increased safety

Dual synthesis of Petri net based application specific logic controllers with increased safety

9 PeNLogic – System for Concurrent Logic Controllers Design

Dual Simulation of Application Specific Logic Controllers Based on Petri Nets

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