In this paper a new method of Petri net array-based synthesis is proposed. The method is based on the structured encoding of places by means of using minimal numbers of bits together with parallel decomposition of a digital system. State machine subnets, which are determined by colors are attached to places and transitions. Colored microoperations which are assigned to places are written into distributed and flexible memory. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs.
The paper presents an application of UML technology in a discrete system development process. In the process at the analysis stage UML diagrams are fundamental tool. The outcome of this stage is a basis for formal models exploited at the design stage, where the design is symbolically verified and treated as a rule-based system. Two formal models of good graphical appeal are proposed: Petri nets and state machine diagrams. Both are heavily using Boolean expressions what makes that design can easily be implemented in modern programmable structures.
Synthesis of FSMs Based on Architectural Decomposition with Joined Multiple EncodingThe method of synthesis of the logic circuit of finite state machine (FSM) with Mealy's outputs is proposed in this paper. Proposed method is based on the innovate encoding of microinstructions split into subsets. Code of microinstruction is represented as a part of current state code and code of microinstruction inside of current subset. It leads to realization of FSM as s double-level structure. It leads to diminishing of number of variables required for encoding of microinstructions. Such approach permits to decrease the number of required outputs of combinational part of FSM.
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