Synthesis of Petri nets into FPGA with operation flexible memories

Abstract

In this paper a new method of Petri net array-based synthesis is proposed. The method is based on the structured encoding of places by means of using minimal numbers of bits together with parallel decomposition of a digital system. State machine subnets, which are determined by colors are attached to places and transitions. Colored microoperations which are assigned to places are written into distributed and flexible memory. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs.

Synthesis of Macro Petri Nets into FPGA with Distributed Memories

“…If any macro place is colored by more than one color it is replaced by its double in followings SM-subnets. In comparison with method where the colored Petri net is an entry point to the synthesis method [26], now, there is required to apply procedure od macroplaces expansion less times than procedure of places merging when Petri net is considered. Now, also outputs are partitioned by colors and each output belongs only to one SM-subnet.…”

Dual synthesis of Petri net based application specific logic controllers with increased safety

“…Operations assigned to places are stored in single memory. The memory could be of partitioned into flexible concurrent parts [17]. The logic circuit is realized as distributed two-level architecture (Fig.…”

“…The first synthesis method is based on modular and symbolic encoding during the logic synthesis [15]. The second one is based on architectural decomposition of a logic circuit [16] and decomposition of Petri net into state machine subnets [16,17], in which the embedded memory blocks are utilized during synthesis process [4,8,[16][17][18]. As a result of both synthesis methods, HDL models are obtained.…”

Structured Mapping of Petri Net States and Events for FPGA Implementations

“…Meanwhile, loaded containers are transported (signal y 12 ) to a proper location indicated by sensor x 13 . When the ingredients are ready it is signalized by preparation of the drink is finished x 10 filling off the first tank is finished x 11 filling off the second tank is finished x 12 the carriage is in its initial location x 13 the carriage is in its target location OUTPUTS Signal Description y 1 preparation of the first ingredient y 2 preparation of the second ingredient y 3 loading containers y 4 mixing ingredients y 5 valve for emptying the first container y 6 valve for emptying the second container y 7 valve for filling the first tank y 8 valve for filling the second tank y 9 carriage movement to the initial location (right) y 10 valve for filling the first container y 11 valve for filling the second container y 12 carriage movement to the target location (left)…”

“…Several optimization techniques could be used for getting smaller number of macrocells [1], [2], [4], [13]. One of them is decomposition of the net into coordinated state machine components, presented in this paper.In that case the number of registered cells (extended T Flip-Flops) could be reduced to nine or even more (Sections VIII, IX).…”