Implementation of Low Power Inverter using Si1-xGex Pocket N &amp; P-Channel Junction-Less Double Gate TFET

Bhattacharya, Sabitabrata; Tripathi, Suman Lata

doi:10.1007/s12633-021-01628-w

Cited by 12 publications

(4 citation statements)

References 31 publications

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“…The most effective way of reducing power dissipation is to lower the threshold and power supply voltages. Another alternate solution in term of nonconventional design methods such as Level shifters, sub-threshold MOSFETs, bulk-driven MOSFETs, and floating gate MOSFETs have reported in the literature [12][13][14]27]. Out of these, FGMOS has the distinct benefit of tunability of the threshold voltage, which may be reduced from its traditional value, making it appropriate for low voltage low power applications.…”

Section: Review Of Cntfet and Fgmos Technologymentioning

confidence: 99%

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Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Sharma,

Jhamb

2024

Eng. Res. Express

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Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442nW and 0.323nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

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Section: Review Of Cntfet and Fgmos Technologymentioning

confidence: 99%

“…The literature also introduces a tunnel field-effect transistor (TFET) as a highly efficient and low-power alternative to MOSFETs. TFET devices exhibit significantly lower power consumption during state transitions compared to MOS devices, making them more efficient switches, as emphasized in [13].…”

Section: Introduction 1overview Of Nand and Nor Gatementioning

confidence: 99%

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Sharma,

Jhamb

2024

Eng. Res. Express

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“…The advanced MOSFET other than conventional NMOS and PMOS can be used to design SAR ADC architecture for future performance improvements. Mostly advanced MOSFETs like Vertical channel MOSFET, FinFET, nanowire or TFET [44][45][46] are explored for digital logic application. So, there is scope to use such efficient transistors for future analog circuit design and applications.…”

Section: Performance Specifications Of Presented Design Of Sar Adcmentioning

confidence: 99%

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

Singh,

Tripathi,

Kumar

2024

JICS

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In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.

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“…For the past five decades, the scaling down of complementary metal-oxide semiconductor (CMOS) technology has been completely achieved by scaling down their physical dimensions and increasing device switching speed in accordance with Moore's law. Thus, maintaining the off-state power consumption for metal oxide semiconductor (MOS) devices became exceedingly challenging [1], [2]. Advanced CMOS technology is moving toward the development of shorter, thinner gate oxides.…”

Section: Introductionmentioning

confidence: 99%

Optimization of 14 nm double gate Bi-GFET for lower leakage current

Nizam

Hamid²,

Salehuddin³

et al. 2023

TELKOMNIKA

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In recent years, breakthroughs in electronics technology have upgraded the physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward smaller sizes and improvements in both quality and performance. Hence, the growth field effect transistor (GFET) is being promoted as one of the worthy candidates due to its superior material characteristics. A 14 nm horizontal double-gate bilayer graphene field effect transistor (FET) utilizing high-k and a metal gate, which are composed of hafnium dioxide (HfO2) and tungsten silicide (WSix) respectively. Silvaco ATHENA and ATLAS technology computer-aided design (TCAD) tools are used to simulate the design and electrical properties, while Taguchi L9 orthogonal arrays (OA) are used to optimize the electrical properties. The threshold voltage (VTH) adjustment implant dose, VTH adjustment implant energy, source/drain (S/D) implant dose, and S/D implant energy have all been investigated as process parameters, while the VTH adjustment tilt angle and the S/D implant tilt angle have been investigated as noise factors. When compared to the initial findings before optimization, the IOFF has a value of 29.579 nA/µm, indicating a significant improvement. Findings from the optimization technique demonstrate excellent device performance with an IOFF of 28.564 nA/µm, which is closer to the international technology roadmap for semiconductors (ITRS) 2013 target.

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Implementation of Low Power Inverter using Si1-xGex Pocket N & P-Channel Junction-Less Double Gate TFET

Cited by 12 publications

References 31 publications

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

Optimization of 14 nm double gate Bi-GFET for lower leakage current

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