High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction
Tejender Singh,
Suman Lata Tripathi,
Vikram Kumar
Abstract:In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures,… Show more
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