Implementation of homeostasis functionality in neuron circuit using double-gate device for spiking neural network

Woo, Sung Yun; Choi, Kyungmin; Kim, Jangsaeng; Kang, Won-Mook; Kim, Chul-Heung; Seo, Young-Tak; Bae, Jong-Ho; Park, Byung‐Gook; Lee, Jong-Ho

doi:10.1016/j.sse.2019.107741

Cited by 16 publications

(14 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The Vth difference of the two PF neuron devices on the same die is less than 0.04 V. By adjusting the Vth of the PF neuron by means of a VG3 control strategy or PGM/ERS operation, the Vth variation of neurons can be reduced and the accuracy of the spike rate of the target neuron can be improved. Also, it is possible to mimic the homeostasis function of biological neurons, which is essential in spiking neural networks (SNNs) based on spike-timingdependent-plasticity (STDP) to improve performances [25,26]. T ox = 10 nm L p = 0.7 m Fig.…”

Section: Siomentioning

confidence: 99%

See 1 more Smart Citation

Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems

et al. 2020

Self Cite

View full text Add to dashboard Cite

A positive-feedback (PF) neuron device capable of threshold tuning and simultaneously processing excitatory (G +) and inhibitory (G-) signals is experimentally demonstrated to replace conventional neuron circuits, for the first time. Thanks to the PF operation, the PF neuron device with steep switching characteristics can implement integrate-and-fire (IF) function of neurons with low-energy consumption. The structure of the PF neuron device efficiently merges a gated PNPN diode and a single MOSFET. Integrateand-fire (IF) operation with steep subthreshold swing (SS < 1 mV/dec) is experimentally implemented by carriers accumulated in an n floating body of the PF neuron device. The carriers accumulated in the n floating body are discharged by an inhibitory signal applied to the merged FET. Moreover, the threshold voltage (Vth) of the proposed PF neuron is controlled by using a charge storage layer. The low-energy consuming PF neuron circuit (~ 0.62 pJ/spike) consists of one PF device and only five MOSFETs for the IF and reset operation. In a high-level system simulation, a deep-spiking neural network (D-SNN) based on PF neurons with four hidden layers (1024 neurons in each layer) shows high-accuracy (98.55%) during a MNIST classification task. The PF neuron device provides a viable solution for high-density and low-energy neuromorphic systems.

show abstract

Section: Siomentioning

confidence: 99%

“…The PF neuron device maintains the nonvolatile of two Vths. The G variation of synaptic devices and the Vth variation of neuron circuits can affect the spike rate of target neurons, which can degrade the performance of HNNs[25,26].Fig. 6 (d)presents the number of dies, showing the difference in the Vth of two PF neuron devices on the same die.…”

mentioning

confidence: 99%

Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems

et al. 2020

Self Cite

View full text Add to dashboard Cite

show abstract

“…24 From another point of view, neuronal inhibition and tunability of ring threshold voltage are important for an energy e cient and reliable neural network. [25][26][27] However, the memristor neurons cannot self-function for control of neuronal inhibition and ring threshold voltage due to the lack of controllability.…”

Section: Introductionmentioning

confidence: 99%

Co-integration of single transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware

Han

Yun

et al. 2021

Preprint

View full text Add to dashboard Cite

Co-integration of multi-state single transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide-semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide-semiconductor field-effect transistor (MOSFET) with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to co-integrate the neurons and synapses with additional CMOS circuits, such as a current mirror and inverter. Such co-integration can enhance packing density, reduce chip cost, and simplify fabrication procedures. Neuronal inhibition and tunability of the firing threshold voltage were demonstrated for an energy efficient and reliable neural network. The multi-state single transistor neuron with low peak power consumption of 120 nW that can control neuronal inhibition and the firing threshold voltage was achieved. Spatio-temporal neuronal functionalities are demonstrated with analyses of a fabricated neuromorphic module, which is composed of a single transistor neuron and a set of single transistor synapse. Image processing for letter pattern recognition and face image recognition is performed using a hardware-based circuit simulation and a software-based neuromorphic simulation, respectively.

show abstract

“…However, there is a downside in using conventional flash arrays since require complex external controllers to implement online learning. For this reason, some researchers devised a double-gated synaptic transistor to easily implement online learning such as spike timing-dependent plasticity [15], [40]. The double-gated synaptic transistor mentioned above can realize online learning and lifelong learning, which are the major advantages of hardware-based neuromorphic systems.…”

Section: Introductionmentioning

confidence: 99%

“…Conventional double-gated synaptic devices use output pulse of presynaptic neuron as current source to prevent drain current flowing when only teaching signal is given. However, this method makes the presynaptic neuron to drive an excessive amount of current, causing a fan-out problem [37][38][39][40][41][42]. For example, transmitting spike to one thousand synaptic devices which operate at 1uA each, will require the presynaptic neuron to drive 1mA of current.…”

Section: Introductionmentioning

confidence: 99%

Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning

et al. 2020

Self Cite

View full text Add to dashboard Cite

In this paper, we propose a floating-gate-based synaptic transistor with two independent control gates that implement both offline and online learning. Unlike previous research on double-gated synaptic transistors, the proposed device is capable of online learning without facing a fan-out problem. Basic operation of the device was verified and a program/erase scheme based on Fowler-Northeim tunneling is suggested for the multi-conductance utilization of the synaptic device. With the proposed P/E scheme, an offline-trained single-layered hardware-based spiking neural network was simulated for MNIST classification, resulting in 87.37% classification accuracy with 10% conductance variation. To alleviate this performance degradation, the online learning method is applied on the offline-trained SNN by reusing 3,000 training images. The effectiveness of the proposed method is also verified under existence of the synaptic weight variance. As a result, up to 86.89% of the performance degradation is alleviated.

show abstract

Implementation of homeostasis functionality in neuron circuit using double-gate device for spiking neural network

Cited by 16 publications

References 16 publications

Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems

Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems

Co-integration of single transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware

Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning

Contact Info

Product

Resources

About