Implementation of double arbiter PUF and its performance evaluation on FPGA

Machida, Takanori; Yamamoto, Daisuke; Iwamoto, Mitsugu; Sakiyama, Kazuo

doi:10.1109/aspdac.2015.7058919

Cited by 43 publications

(38 citation statements)

References 3 publications

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“…The uniqueness of [43] is 36.75% in a different evaluation method, in which the ideal uniqueness value is 100% other than 50%, that is commonly utilized. The uniqueness results for the conventional APUF implemented on FPGA are 4.70% by [42], 7.20% by [44] and 9.42% by [11], respectively. The 2-1 double APUF and 3-1 double APUF, which mix two or three APUFs to generate one 1-bit response, achieve higher uniqueness [42] but have to sacrifice reliability.…”

Section: Reliabilitymentioning

confidence: 95%

“…The uniqueness results for the conventional APUF implemented on FPGA are 4.70% by [42], 7.20% by [44] and 9.42% by [11], respectively. The 2-1 double APUF and 3-1 double APUF, which mix two or three APUFs to generate one 1-bit response, achieve higher uniqueness [42] but have to sacrifice reliability. [35] achieves higher uniqueness results when introducing tuning circuits.…”

Section: Reliabilitymentioning

confidence: 95%

See 1 more Smart Citation

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation

Liu

Cui

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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A PUF is a physical security primitive that allows to extract intrinsic digital identifiers from electronic devices. It is a promising candidate to improve security in lightweight devices targeted at IoT applications due to its low cost nature. The Arbiter PUF or APUF has been widely studied in the technical literature. However it often suffers from disadvantages such as poor uniqueness and reliability, particularly when implemented on FPGAs due to physical layout restrictions. To address these problems, a new design known as FF-APUF has been proposed; it offers a compact architecture, combined with good uniqueness and reliability properties, and is well suited to FPGA implementation. Many PUF designs have been shown to be vulnerable to machine learning (ML) based modelling attacks. In this paper, initial tests show that to attack the FF-APUF design requires more effort for the adversary than a conventional APUF design. A comprehensive analysis of the experimental results for the FF-APUF design is presented to show this outcome. An improved APUF design with a balanced routing, and the proposed FF-APUF design are both implemented on an Xilinx Artix-7 FPGA at 28 nm technology. The empirical min-entropy of the FF-APUF design across different devices is shown to be more than twice that of the conventional APUF design.

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Section: Reliabilitymentioning

confidence: 95%

Section: Reliabilitymentioning

confidence: 95%

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation

Liu

Cui

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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“…Moudgil et al [19] proposed a circuit-based technique for detecting counterfeits. Some other scholars [20] tried to apply machine learning-based approach with statistical techniques to detect counterfeits. Most statistical-related approaches were based on the data analysis deriving from old data.…”

Section: Introductionmentioning

confidence: 99%

Anti-Counterfeit Scheme Using Monte Carlo Simulation for E-commerce in Cloud Systems

Gai

Qiu

Zhao

et al. 2015

2015 IEEE 2nd International Conference on Cyber Security and Cloud Computing

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E-commerce using cloud-based trading platforms has become a popular approach with the growth of global development in recent years. However, the existence of counterfeits on the platform has threatened the benefits of all stakeholders. This paper proposes a novel scheme named Anti-Counterfeit Deterministic Prediction Model (ADPM), which is designed for detecting counterfeits by using Monte Carlo Model (MCM) to predict the potential malicious information in e-commerce. We consider the discriminations of the fake merchandises a crucial issue in preventing counterfeits on the online business platforms. The proposed mechanism provides a paradigm of machine-learning with using a novel algorithm that derives from MCM. The main algorithm used in our proposed mechanism is Monte Carlo Model-based Prediction Analysis Algorithm (M-PAA). Our experiment has evaluated that the proposed approach can provision the predictions of the insecure information in e-commerce.

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“…Many existing PUFs, such as ring oscillator (RO) [9][10][11] and arbiter-based [7,12] designs, are complex and hard to integrate for device manufacturers into their application ICs, due to great design overheads or poor performance in security metrics. In the past years, analog-based PUF circuits have been proposed that use lower complexity circuit designs while achieving very good results in PUF security metrics.…”

Section: Introductionmentioning

confidence: 99%

Embedded Analog Physical Unclonable Function System to Extract Reliable and Unique Security Keys

et al. 2020

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Internet of Things (IoT) enabled devices have become more and more pervasive in our everyday lives. Examples include wearables transmitting and processing personal data and smart labels interacting with customers. Due to the sensitive data involved, these devices need to be protected against attackers. In this context, hardware-based security primitives such as Physical Unclonable Functions (PUFs) provide a powerful solution to secure interconnected devices. The main benefit of PUFs, in combination with traditional cryptographic methods, is that security keys are derived from the random intrinsic variations of the underlying core circuit. In this work, we present a holistic analog-based PUF evaluation platform, enabling direct access to a scalable design that can be customized to fit the application requirements in terms of the number of required keys and bit width. The proposed platform covers the full software and hardware implementations and allows for tracing the PUF response generation from the digital level back to the internal analog voltages that are directly involved in the response generation procedure. Our analysis is based on 30 fabricated PUF cores that we evaluated in terms of PUF security metrics and bit errors for various temperatures and biases. With an average reliability of 99.20% and a uniqueness of 48.84%, the proposed system shows values close to ideal.

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Implementation of double arbiter PUF and its performance evaluation on FPGA

Cited by 43 publications

References 3 publications

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation

Anti-Counterfeit Scheme Using Monte Carlo Simulation for E-commerce in Cloud Systems

Embedded Analog Physical Unclonable Function System to Extract Reliable and Unique Security Keys

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