Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices

Boubaker, Mohamed; Akil, Mohamed; Khalifa, Khaled Ben; Grandpierre, Thierry; Bedoui, Mohamed Hédi

doi:10.1007/s00521-009-0296-5

Cited by 15 publications

(15 citation statements)

References 9 publications

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“…The proposed work improves the hardware performance of some related works [10, 12, 13, 26, 27]. At first, we compared the attained performances for the same application (23 × 25) LVQ NN.…”

Section: Comparison To Related Workmentioning

confidence: 95%

“…Therefore, to improve our adopted architecture latency, we can later partition the algorithm into two parts: one to be implemented in software and another one in the hardware. The proposed work improves the hardware performance of some related works [10,12,13,26,27]. At first, we compared the attained performances for the same application (23 × 25) LVQ NN.…”

Section: Comparison To Related Workmentioning

confidence: 97%

“…At first, we compared the attained performances for the same application (23 × 25) LVQ NN. The occupied area is 40% compared with [10] and 50% compared with [13]. Nevertheless, their presented areas are only for the decision phase.…”

Section: Comparison To Related Workmentioning

confidence: 99%

“…In the present work, investigations on a possible low power and an optimised area architecture for LVQ neural network algorithm are performed. This architecture will be integrated later in a SOC to detect patient vigilance states after an analysis of the electro-encephalographic signals [10].…”

Section: Introduction and Related Workmentioning

confidence: 99%

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Implementation of a low‐power LVQ architecture on FPGA

Najoua

Boubaker

Bedoui

2017

IET Circuits, Devices & Syst

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This study presents an architecture-optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy consumption. The low-power/energy architecture is obtained through the selection of the best one amongst a number of architectures produced by FPGA software design tools that combine power, area and the ergonomic utilisation of internal FPGA resources. A complete characterisation of power at the architectural level was carried out using the Xpower tool. An analytical power model was determined by the following parameters: area, delay and LVQ topology. Concerning the authors' architecture, there is a 28% gain in the area design. Moreover, it consumes 8% power in the nanoboard 3000 compared with the other ones.

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“…The proposed work improves the hardware performance of some related works [10, 12, 13, 26, 27]. At first, we compared the attained performances for the same application (23 × 25) LVQ NN.…”

Section: Comparison To Related Workmentioning

confidence: 95%

Section: Comparison To Related Workmentioning

confidence: 97%

Section: Comparison To Related Workmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Implementation of a low‐power LVQ architecture on FPGA

Najoua

Boubaker

Bedoui

2017

IET Circuits, Devices & Syst

Self Cite

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“…al. 20 presented the implemented of LVQ (Learning Vector Quantization) neural network on FPGA. Savich et.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Wavelet Neural Network Training with PSO/iPSO

Şahin

Çavuşlu

2018

J CIRCUIT SYST COMP

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In this study, field-programmable gate array (FPGA)-based hardware implementation of the wavelet neural network (WNN) training using particle swarm optimization (PSO) and improved particle swarm optimization (iPSO) algorithms are presented. The WNN architecture and wavelet activation function approach that is proper for the hardware implementation are suggested in the study. Using the suggested architecture and training algorithms, test operations are implemented on two different dynamic system recognition problems. From the test results obtained, it is observed that WNN architecture generalizes well and the activation function suggested has approximately the same success rate with the wavelet function defined in the literature. In the FPGA-based implementation, IEEE 754 floating-point number format is used. Experimental tests are done on Xilinx Artix 7 xc7a100t-1csg324 using ISE Webpack 14.7 program.

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