Implementation of adder structure with fast carry network for high speed processor

Anand, N; Joseph, George; Raj, Johny S; Jayakrishnan, P.

doi:10.1109/icgce.2013.6823425

2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE) 2013

DOI: 10.1109/icgce.2013.6823425

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Implementation of adder structure with fast carry network for high speed processor

N Anand

George Joseph

Johny S Raj

et al.

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Cited by 3 publications

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Implementation of efficient portable low delay adder using FPGA

Barakat¹,

Saad

Shokair

et al. 2016

2016 28th International Conference on Microelectronics (ICM)

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Implementation of adder structure with fast carry network for high speed processor

Cited by 3 publications

References 9 publications

Implementation of efficient portable low delay adder using FPGA

Implementation of efficient portable low delay adder using FPGA

High Speed Power Efficient Carry Select Adder Design

Kogge Stone Adder with GDI technique in 130nm technology for high performance DSP applications

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